IP_BASE 42 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, IP_BASE 39 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x00012460, 0x00408C00, 0, 0, 0 } }, IP_BASE 47 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE CLK_BASE ={ { { { 0x000120C0, 0x00016C00, 0x00401800, 0, 0, 0 } }, IP_BASE 55 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x000125C0, 0x0040B800, 0, 0, 0 } }, IP_BASE 63 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE FUSE_BASE ={ { { { 0x000120A0, 0x00017400, 0x00401400, 0, 0, 0 } }, IP_BASE 71 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x00012160, 0x00402C00, 0, 0 } }, IP_BASE 79 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x00012520, 0x0040A400, 0, 0, 0 } }, IP_BASE 87 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE MMHUB_BASE ={ { { { 0x00012440, 0x0001A000, 0x00408800, 0, 0, 0 } }, IP_BASE 95 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, IP_BASE 103 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, IP_BASE 111 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x00012D80, 0x0041B000 } }, IP_BASE 119 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x00012500, 0x0040A000, 0, 0, 0 } }, IP_BASE 127 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE PCIE0_BASE ={ { { { 0x000128C0, 0x00411800, 0x04440000, 0, 0, 0 } }, IP_BASE 135 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x00012540, 0x0040A800, 0, 0, 0 } }, IP_BASE 143 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE SDMA1_BASE ={ { { { 0x00001860, 0x00012560, 0x0040AC00, 0, 0, 0 } }, IP_BASE 151 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE SDMA2_BASE ={ { { { 0x00013760, 0x0001E000, 0x0042EC00, 0, 0, 0 } }, IP_BASE 159 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE SDMA3_BASE ={ { { { 0x00013780, 0x0001E400, 0x0042F000, 0, 0, 0 } }, IP_BASE 167 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE SDMA4_BASE ={ { { { 0x000137A0, 0x0001E800, 0x0042F400, 0, 0, 0 } }, IP_BASE 175 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE SDMA5_BASE ={ { { { 0x000137C0, 0x0001EC00, 0x0042F800, 0, 0, 0 } }, IP_BASE 183 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE SDMA6_BASE ={ { { { 0x000137E0, 0x0001F000, 0x0042FC00, 0, 0, 0 } }, IP_BASE 191 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE SDMA7_BASE ={ { { { 0x00013800, 0x0001F400, 0x00430000, 0, 0, 0 } }, IP_BASE 199 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } }, IP_BASE 205 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } }, IP_BASE 211 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE UMC_BASE ={ { { { 0x000132C0, 0x00014000, 0x00425800, 0, 0, 0 } }, IP_BASE 219 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE UVD_BASE ={ { { { 0x00007800, 0x00007E00, 0x00012180, 0x00403000, 0, 0 } }, IP_BASE 227 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE DBGU_IO_BASE ={ { { { 0x000001E0, 0x000125A0, 0x0040B400, 0, 0, 0 } }, IP_BASE 235 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE RSMU_BASE ={ { { { 0x00012000, 0, 0, 0, 0, 0 } }, IP_BASE 37 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0, 0, 0, 0, 0 } }, IP_BASE 43 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x00017E00, 0x0001B000 } }, IP_BASE 49 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0, 0, 0, 0, 0 } }, IP_BASE 55 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE DCN_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0, 0 } }, IP_BASE 61 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0, 0, 0, 0, 0 } }, IP_BASE 67 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0, 0, 0, 0 } }, IP_BASE 73 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0, 0, 0, 0, 0 } }, IP_BASE 79 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } }, IP_BASE 85 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, IP_BASE 91 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, IP_BASE 97 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } }, IP_BASE 103 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0, 0, 0, 0, 0 } }, IP_BASE 109 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0, 0 } }, IP_BASE 115 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } }, IP_BASE 121 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } }, IP_BASE 127 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0, 0, 0, 0, 0 } }, IP_BASE 133 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE VCN_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0, 0 } }, IP_BASE 39 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0x02408C00, 0, 0, 0 } }, IP_BASE 46 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } }, IP_BASE 53 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } }, IP_BASE 60 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } }, IP_BASE 67 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, IP_BASE 74 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, IP_BASE 81 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } }, IP_BASE 88 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, IP_BASE 95 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE HDA_BASE ={ { { { 0x004C0000, 0x02404800, 0, 0, 0 } }, IP_BASE 102 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } }, IP_BASE 109 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } }, IP_BASE 116 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } }, IP_BASE 123 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00E80000, 0x00EC0000, 0x00F00000, 0x02400400 } }, IP_BASE 130 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } }, IP_BASE 137 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } }, IP_BASE 144 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000, 0, 0, 0 } }, IP_BASE 151 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE SDMA_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, IP_BASE 158 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } }, IP_BASE 165 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } }, IP_BASE 172 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } }, IP_BASE 179 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } }, IP_BASE 186 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } }, IP_BASE 39 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0x02408C00, 0, 0, 0 } }, IP_BASE 46 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } }, IP_BASE 53 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } }, IP_BASE 60 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } }, IP_BASE 67 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, IP_BASE 74 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, IP_BASE 81 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } }, IP_BASE 88 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, IP_BASE 95 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE HDA_BASE ={ { { { 0x004C0000, 0x02404800, 0, 0, 0 } }, IP_BASE 102 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } }, IP_BASE 109 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } }, IP_BASE 116 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } }, IP_BASE 123 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } }, IP_BASE 130 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } }, IP_BASE 137 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } }, IP_BASE 144 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE PCIE0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } }, IP_BASE 151 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE SDMA_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, IP_BASE 158 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } }, IP_BASE 165 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } }, IP_BASE 172 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } }, IP_BASE 179 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } }, IP_BASE 186 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } }, IP_BASE 39 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE ACP_BASE ={ { { { 0x02403800, 0x00480000, 0, 0, 0 } }, IP_BASE 46 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x02408C00, 0, 0, 0 } }, IP_BASE 53 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017E00, 0 } }, IP_BASE 60 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE DBGU_IO0_BASE ={ { { { 0x000001E0, 0x0240B400, 0, 0, 0 } }, IP_BASE 67 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } }, IP_BASE 74 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } }, IP_BASE 81 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, IP_BASE 88 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, IP_BASE 95 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } }, IP_BASE 102 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x02402C00, 0, 0 } }, IP_BASE 109 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE HDA_BASE ={ { { { 0x02404800, 0x004C0000, 0, 0, 0 } }, IP_BASE 116 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } }, IP_BASE 123 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE IOHC0_BASE ={ { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0 } }, IP_BASE 130 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE ISP_BASE ={ { { { 0x00018000, 0x0240B000, 0, 0, 0 } }, IP_BASE 137 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE L2IMU0_BASE ={ { { { 0x00007DC0, 0x02407000, 0x00900000, 0x04FC0000, 0x055C0000 } }, IP_BASE 144 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } }, IP_BASE 151 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000 } }, IP_BASE 158 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x02400400, 0x00E80000, 0x00EC0000, 0x00F00000 } }, IP_BASE 165 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } }, IP_BASE 172 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } }, IP_BASE 179 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000, 0, 0, 0 } }, IP_BASE 186 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x0240A800, 0, 0, 0 } }, IP_BASE 193 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0 } }, IP_BASE 200 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } }, IP_BASE 207 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } }, IP_BASE 214 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } }, IP_BASE 221 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } }, IP_BASE 38 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, IP_BASE 43 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, IP_BASE 48 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, IP_BASE 53 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, IP_BASE 58 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, IP_BASE 63 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, IP_BASE 68 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE MP2_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, IP_BASE 73 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0, 0, 0, 0 } }, IP_BASE 78 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, IP_BASE 83 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, IP_BASE 88 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE DBGU_BASE = { { { { 0x00000180, 0x000001A0, 0, 0, 0 } }, IP_BASE 93 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE DBGU_NBIO_BASE = { { { { 0x000001C0, 0, 0, 0, 0 } }, IP_BASE 98 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE DBGU_IO_BASE = { { { { 0x000001E0, 0, 0, 0, 0 } }, IP_BASE 103 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE DFX_DAP_BASE = { { { { 0x000005A0, 0, 0, 0, 0 } }, IP_BASE 108 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE DFX_BASE = { { { { 0x00000580, 0, 0, 0, 0 } }, IP_BASE 113 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0, 0, 0, 0 } }, IP_BASE 118 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE SYSTEMHUB_BASE = { { { { 0x00000EA0, 0, 0, 0, 0 } }, IP_BASE 123 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE L2IMU_BASE = { { { { 0x00007DC0, 0, 0, 0, 0 } }, IP_BASE 128 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE IOHC_BASE = { { { { 0x00010000, 0, 0, 0, 0 } }, IP_BASE 133 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0, 0, 0, 0 } }, IP_BASE 138 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE VCE_BASE = { { { { 0x00007E00, 0x00048800, 0, 0, 0 } }, IP_BASE 143 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0, 0, 0 } }, IP_BASE 148 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0 } }, IP_BASE 153 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0 } }, IP_BASE 158 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0 } }, IP_BASE 163 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0 } }, IP_BASE 168 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0, 0, 0, 0 } }, IP_BASE 173 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE SDMA1_BASE = { { { { 0x00001460, 0, 0, 0, 0 } }, IP_BASE 178 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE XDMA_BASE = { { { { 0x00003400, 0, 0, 0, 0 } }, IP_BASE 183 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0 } }, IP_BASE 188 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } }, IP_BASE 193 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0, 0, 0, 0 } }, IP_BASE 198 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE PWR_BASE = { { { { 0x00016A00, 0, 0, 0, 0 } }, IP_BASE 203 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } }, IP_BASE 208 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0, 0, 0, 0 } }, IP_BASE 39 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0, 0, 0, 0, 0 } }, IP_BASE 45 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x0001B000, 0x0001B200 } }, IP_BASE 51 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE DCE_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0, 0 } }, IP_BASE 57 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0, 0, 0, 0, 0 } }, IP_BASE 63 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0, 0, 0, 0, 0 } }, IP_BASE 69 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0, 0, 0, 0 } }, IP_BASE 75 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0, 0, 0, 0, 0 } }, IP_BASE 81 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } }, IP_BASE 87 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, IP_BASE 93 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, IP_BASE 99 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } }, IP_BASE 105 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0, 0, 0, 0, 0 } }, IP_BASE 111 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0, 0, 0, 0, 0 } }, IP_BASE 117 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE SDMA1_BASE ={ { { { 0x00001860, 0, 0, 0, 0, 0 } }, IP_BASE 123 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } }, IP_BASE 129 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } }, IP_BASE 135 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0, 0, 0, 0, 0 } }, IP_BASE 141 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE UVD_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0, 0 } }, IP_BASE 148 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE VCE_BASE ={ { { { 0x00007E00/* 0x00008800 */, 0, 0, 0, 0, 0 } }, IP_BASE 154 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE XDMA_BASE ={ { { { 0x00003400, 0, 0, 0, 0, 0 } }, IP_BASE 160 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE RSMU_BASE ={ { { { 0x00012000, 0, 0, 0, 0, 0 } },