IPU_CM_REG         32 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_CONF			IPU_CM_REG(0)
IPU_CM_REG         34 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_SRM_PRI1			IPU_CM_REG(0x00a0)
IPU_CM_REG         35 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_SRM_PRI2			IPU_CM_REG(0x00a4)
IPU_CM_REG         36 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_FS_PROC_FLOW1		IPU_CM_REG(0x00a8)
IPU_CM_REG         37 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_FS_PROC_FLOW2		IPU_CM_REG(0x00ac)
IPU_CM_REG         38 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_FS_PROC_FLOW3		IPU_CM_REG(0x00b0)
IPU_CM_REG         39 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_FS_DISP_FLOW1		IPU_CM_REG(0x00b4)
IPU_CM_REG         40 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_FS_DISP_FLOW2		IPU_CM_REG(0x00b8)
IPU_CM_REG         41 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_SKIP			IPU_CM_REG(0x00bc)
IPU_CM_REG         42 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_DISP_ALT_CONF		IPU_CM_REG(0x00c0)
IPU_CM_REG         43 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_DISP_GEN			IPU_CM_REG(0x00c4)
IPU_CM_REG         44 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_DISP_ALT1			IPU_CM_REG(0x00c8)
IPU_CM_REG         45 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_DISP_ALT2			IPU_CM_REG(0x00cc)
IPU_CM_REG         46 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_DISP_ALT3			IPU_CM_REG(0x00d0)
IPU_CM_REG         47 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_DISP_ALT4			IPU_CM_REG(0x00d4)
IPU_CM_REG         48 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_SNOOP			IPU_CM_REG(0x00d8)
IPU_CM_REG         49 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_MEM_RST			IPU_CM_REG(0x00dc)
IPU_CM_REG         50 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_PM				IPU_CM_REG(0x00e0)
IPU_CM_REG         51 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_GPR				IPU_CM_REG(0x00e4)
IPU_CM_REG         52 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_CHA_DB_MODE_SEL(ch)		IPU_CM_REG(0x0150 + 4 * ((ch) / 32))
IPU_CM_REG         53 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_ALT_CHA_DB_MODE_SEL(ch)	IPU_CM_REG(0x0168 + 4 * ((ch) / 32))
IPU_CM_REG         54 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_CHA_CUR_BUF(ch)		IPU_CM_REG(0x023C + 4 * ((ch) / 32))
IPU_CM_REG         55 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_ALT_CUR_BUF0		IPU_CM_REG(0x0244)
IPU_CM_REG         56 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_ALT_CUR_BUF1		IPU_CM_REG(0x0248)
IPU_CM_REG         57 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_SRM_STAT			IPU_CM_REG(0x024C)
IPU_CM_REG         58 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_PROC_TASK_STAT		IPU_CM_REG(0x0250)
IPU_CM_REG         59 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_DISP_TASK_STAT		IPU_CM_REG(0x0254)
IPU_CM_REG         60 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_CHA_BUF0_RDY(ch)		IPU_CM_REG(0x0268 + 4 * ((ch) / 32))
IPU_CM_REG         61 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_CHA_BUF1_RDY(ch)		IPU_CM_REG(0x0270 + 4 * ((ch) / 32))
IPU_CM_REG         62 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_CHA_BUF2_RDY(ch)		IPU_CM_REG(0x0288 + 4 * ((ch) / 32))
IPU_CM_REG         63 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_ALT_CHA_BUF0_RDY(ch)	IPU_CM_REG(0x0278 + 4 * ((ch) / 32))
IPU_CM_REG         64 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_ALT_CHA_BUF1_RDY(ch)	IPU_CM_REG(0x0280 + 4 * ((ch) / 32))
IPU_CM_REG         66 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_INT_CTRL(n)		IPU_CM_REG(0x003C + 4 * (n))
IPU_CM_REG         67 drivers/gpu/ipu-v3/ipu-prv.h #define IPU_INT_STAT(n)		IPU_CM_REG(0x0200 + 4 * (n))