IPC_REG_BASE       16 drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h #define IPC_REG_PISR_CHV_AB      (IPC_REG_BASE + 0x00)
IPC_REG_BASE       18 drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h #define IPC_REG_PIMR_CHV_AB      (IPC_REG_BASE + 0x04)
IPC_REG_BASE       21 drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h #define IPC_REG_PISR_BXT	 (IPC_REG_BASE + 0x0C)
IPC_REG_BASE       23 drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h #define IPC_REG_PIMR_BXT	 (IPC_REG_BASE + 0x08)
IPC_REG_BASE       26 drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h #define IPC_REG_ISH_HOST_FWSTS	(IPC_REG_BASE + 0x34)
IPC_REG_BASE       28 drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h #define IPC_REG_HOST_COMM	(IPC_REG_BASE + 0x38)
IPC_REG_BASE       30 drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h #define IPC_REG_ISH_RST		(IPC_REG_BASE + 0x44)
IPC_REG_BASE       33 drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h #define IPC_REG_HOST2ISH_DRBL	(IPC_REG_BASE + 0x48)
IPC_REG_BASE       35 drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h #define IPC_REG_ISH2HOST_DRBL	(IPC_REG_BASE + 0x54)
IPC_REG_BASE       37 drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h #define IPC_REG_ISH2HOST_MSG	(IPC_REG_BASE + 0x60)
IPC_REG_BASE       39 drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h #define IPC_REG_HOST2ISH_MSG	(IPC_REG_BASE + 0xE0)
IPC_REG_BASE       41 drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h #define	IPC_REG_ISH_RMP2	(IPC_REG_BASE + 0x368)
IPC_REG_BASE       43 drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h #define	IPC_REG_MAX		(IPC_REG_BASE + 0x400)