IO_BASE 20 arch/arm/mach-integrator/hardware.h #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE) IO_BASE 712 arch/arm/mach-lpc32xx/lpc32xx.h IO_BASE) IO_BASE 231 arch/arm/mach-rpc/ecard.c src_pgd = pgd_offset(mm, (unsigned long)IO_BASE); IO_BASE 46 arch/arm/mach-rpc/include/mach/hardware.h #define VIDC_BASE (IO_BASE + 0x00400000) IO_BASE 47 arch/arm/mach-rpc/include/mach/hardware.h #define EXPMASK_BASE (IO_BASE + 0x00360000) IO_BASE 48 arch/arm/mach-rpc/include/mach/hardware.h #define ECARD_IOC4_BASE (IO_BASE + 0x00270000) IO_BASE 49 arch/arm/mach-rpc/include/mach/hardware.h #define ECARD_IOC_BASE (IO_BASE + 0x00240000) IO_BASE 50 arch/arm/mach-rpc/include/mach/hardware.h #define IOMD_BASE (IO_BASE + 0x00200000) IO_BASE 51 arch/arm/mach-rpc/include/mach/hardware.h #define IOC_BASE (IO_BASE + 0x00200000) IO_BASE 52 arch/arm/mach-rpc/include/mach/hardware.h #define ECARD_MEMC8_BASE (IO_BASE + 0x0002b000) IO_BASE 53 arch/arm/mach-rpc/include/mach/hardware.h #define FLOPPYDMA_BASE (IO_BASE + 0x0002a000) IO_BASE 54 arch/arm/mach-rpc/include/mach/hardware.h #define PCIO_BASE (IO_BASE + 0x00010000) IO_BASE 55 arch/arm/mach-rpc/include/mach/hardware.h #define ECARD_MEMC_BASE (IO_BASE + 0x00000000) IO_BASE 73 arch/arm/mach-rpc/riscpc.c .virtual = (u32)IO_BASE, IO_BASE 77 arch/m68k/include/asm/apollohw.h #define sio01 ((*(volatile struct SCN2681 *)(IO_BASE + sio01_physaddr))) IO_BASE 78 arch/m68k/include/asm/apollohw.h #define sio23 ((*(volatile struct SCN2681 *)(IO_BASE + sio23_physaddr))) IO_BASE 79 arch/m68k/include/asm/apollohw.h #define rtc (((volatile struct mc146818 *)(IO_BASE + rtc_physaddr))) IO_BASE 80 arch/m68k/include/asm/apollohw.h #define cpuctrl (*(volatile unsigned int *)(IO_BASE + cpuctrl_physaddr)) IO_BASE 81 arch/m68k/include/asm/apollohw.h #define pica (IO_BASE + pica_physaddr) IO_BASE 82 arch/m68k/include/asm/apollohw.h #define picb (IO_BASE + picb_physaddr) IO_BASE 83 arch/m68k/include/asm/apollohw.h #define apollo_timer (IO_BASE + timer_physaddr) IO_BASE 84 arch/m68k/include/asm/apollohw.h #define addr_xlat_map ((unsigned short *)(IO_BASE + 0x17000)) IO_BASE 86 arch/m68k/include/asm/apollohw.h #define isaIO2mem(x) (((((x) & 0x3f8) << 7) | (((x) & 0xfc00) >> 6) | ((x) & 0x7)) + 0x40000 + IO_BASE) IO_BASE 177 arch/mips/include/asm/io.h base = (u64) IO_BASE; IO_BASE 34 arch/mips/include/asm/mach-generic/spaces.h #ifndef IO_BASE IO_BASE 64 arch/mips/include/asm/mach-generic/spaces.h #ifndef IO_BASE IO_BASE 53 arch/mips/include/asm/sibyte/sb1250.h #define IOADDR(a) ((void __iomem *)(IO_BASE + (a))) IO_BASE 62 arch/mips/include/asm/sn/addrs.h #define NODE_IO_BASE(_n) (IO_BASE + NODE_OFFSET(_n)) IO_BASE 37 arch/mips/include/asm/txx9/rbtx4927.h #define RBTX4927_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000) IO_BASE 38 arch/mips/include/asm/txx9/rbtx4927.h #define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000) IO_BASE 39 arch/mips/include/asm/txx9/rbtx4927.h #define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006) IO_BASE 40 arch/mips/include/asm/txx9/rbtx4927.h #define RBTX4927_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000) IO_BASE 41 arch/mips/include/asm/txx9/rbtx4927.h #define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000) IO_BASE 42 arch/mips/include/asm/txx9/rbtx4927.h #define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002) IO_BASE 43 arch/mips/include/asm/txx9/rbtx4927.h #define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006) IO_BASE 44 arch/mips/include/asm/txx9/rbtx4927.h #define RBTX4927_BRAMRTC_BASE (IO_BASE + TXX9_CE(2) + 0x00010000) IO_BASE 45 arch/mips/include/asm/txx9/rbtx4927.h #define RBTX4927_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000) IO_BASE 19 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_FPGA_REG_ADDR (IO_BASE + TXX9_CE(2) + 0x00000000) IO_BASE 20 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_FPGA_REV_ADDR (IO_BASE + TXX9_CE(2) + 0x00000002) IO_BASE 21 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_CONFIG1_ADDR (IO_BASE + TXX9_CE(2) + 0x00000004) IO_BASE 22 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_CONFIG2_ADDR (IO_BASE + TXX9_CE(2) + 0x00000006) IO_BASE 23 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_CONFIG3_ADDR (IO_BASE + TXX9_CE(2) + 0x00000008) IO_BASE 24 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000) IO_BASE 25 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_DIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001002) IO_BASE 26 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_BDIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001004) IO_BASE 27 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000) IO_BASE 28 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_IMASK2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002002) IO_BASE 29 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_INTPOL_ADDR (IO_BASE + TXX9_CE(2) + 0x00002004) IO_BASE 30 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_ISTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006) IO_BASE 31 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_ISTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002008) IO_BASE 32 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200a) IO_BASE 33 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_IMSTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200c) IO_BASE 34 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000) IO_BASE 35 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_PIOSEL_ADDR (IO_BASE + TXX9_CE(2) + 0x00005000) IO_BASE 36 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_SPICS_ADDR (IO_BASE + TXX9_CE(2) + 0x00005002) IO_BASE 37 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_SFPWR_ADDR (IO_BASE + TXX9_CE(2) + 0x00005008) IO_BASE 38 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_SFVOL_ADDR (IO_BASE + TXX9_CE(2) + 0x0000500a) IO_BASE 39 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000) IO_BASE 40 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x00007002) IO_BASE 41 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007004) IO_BASE 42 arch/mips/include/asm/txx9/rbtx4938.h #define RBTX4938_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000) IO_BASE 19 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_IOC_REG_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000) IO_BASE 20 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_BOARD_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000) IO_BASE 21 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_IOC_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000002) IO_BASE 22 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_CONFIG1_ADDR (IO_BASE + TXX9_CE(1) + 0x00000004) IO_BASE 23 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_CONFIG2_ADDR (IO_BASE + TXX9_CE(1) + 0x00000006) IO_BASE 24 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_CONFIG3_ADDR (IO_BASE + TXX9_CE(1) + 0x00000008) IO_BASE 25 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_CONFIG4_ADDR (IO_BASE + TXX9_CE(1) + 0x0000000a) IO_BASE 26 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_USTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00001000) IO_BASE 27 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_UDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001002) IO_BASE 28 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_BDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001004) IO_BASE 29 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_IEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00002000) IO_BASE 30 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_IPOL_ADDR (IO_BASE + TXX9_CE(1) + 0x00002002) IO_BASE 31 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_IFAC1_ADDR (IO_BASE + TXX9_CE(1) + 0x00002004) IO_BASE 32 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_IFAC2_ADDR (IO_BASE + TXX9_CE(1) + 0x00002006) IO_BASE 33 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_SOFTINT_ADDR (IO_BASE + TXX9_CE(1) + 0x00003000) IO_BASE 34 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_ISASTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00004000) IO_BASE 35 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_PCISTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00004002) IO_BASE 36 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_ROME_ADDR (IO_BASE + TXX9_CE(1) + 0x00004004) IO_BASE 37 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_SPICS_ADDR (IO_BASE + TXX9_CE(1) + 0x00004006) IO_BASE 38 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_AUDI_ADDR (IO_BASE + TXX9_CE(1) + 0x00004008) IO_BASE 39 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_ISAGPIO_ADDR (IO_BASE + TXX9_CE(1) + 0x0000400a) IO_BASE 40 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_PE1_ADDR (IO_BASE + TXX9_CE(1) + 0x00005000) IO_BASE 41 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_PE2_ADDR (IO_BASE + TXX9_CE(1) + 0x00005002) IO_BASE 42 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_PE3_ADDR (IO_BASE + TXX9_CE(1) + 0x00005004) IO_BASE 43 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_VP_ADDR (IO_BASE + TXX9_CE(1) + 0x00005006) IO_BASE 44 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_VPRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00005008) IO_BASE 45 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_VPSOUT_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500a) IO_BASE 46 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_VPSIN_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500c) IO_BASE 48 arch/mips/include/asm/txx9/rbtx4939.h (IO_BASE + TXX9_CE(1) + 0x00006000 + (s) * 16 + ((ch) & 3) * 2) IO_BASE 49 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_SOFTRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00007000) IO_BASE 50 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_RESETEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00007002) IO_BASE 51 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_RESETSTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00007004) IO_BASE 52 arch/mips/include/asm/txx9/rbtx4939.h #define RBTX4939_ETHER_BASE (IO_BASE + TXX9_CE(1) + 0x00020000) IO_BASE 676 arch/mips/kernel/setup.c if (UNCAC_BASE != IO_BASE) IO_BASE 134 arch/mips/pci/ops-tx3927.c channel->io_resource->start + mips_io_port_base - IO_BASE; IO_BASE 251 arch/mips/pci/ops-tx4927.c channel->io_map_base - IO_BASE) | IO_BASE 167 arch/mips/sgi-ip27/ip27-init.c set_io_port_base(IO_BASE); IO_BASE 196 arch/mips/txx9/generic/pci.c set_io_port_base(IO_BASE + pcic->mem_resource[1].start); IO_BASE 199 arch/mips/txx9/generic/pci.c pcic->io_map_base = IO_BASE + pcic->mem_resource[1].start; IO_BASE 203 arch/mips/txx9/generic/pci.c io_base - (mips_io_port_base - IO_BASE); IO_BASE 204 arch/mips/txx9/generic/pci.c pcic->io_offset = io_base - (mips_io_port_base - IO_BASE); IO_BASE 176 arch/mips/txx9/jmr3927/setup.c .start = JMR3927_IOC_NVRAMB_ADDR - IO_BASE, IO_BASE 177 arch/mips/txx9/jmr3927/setup.c .end = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1, IO_BASE 193 arch/mips/txx9/jmr3927/setup.c unsigned long iocled_base = JMR3927_IOC_LED_ADDR - IO_BASE; IO_BASE 290 arch/mips/txx9/rbtx4927/setup.c .start = RBTX4927_BRAMRTC_BASE - IO_BASE, IO_BASE 291 arch/mips/txx9/rbtx4927/setup.c .end = RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1, IO_BASE 353 arch/mips/txx9/rbtx4927/setup.c txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL); IO_BASE 358 arch/mips/txx9/rbtx4938/setup.c txx9_iocled_init(RBTX4938_LED_ADDR - IO_BASE, -1, 8, 1, "green", NULL); IO_BASE 46 arch/mips/txx9/rbtx4939/setup.c ((((unsigned long)(addr) - IO_BASE) & 0xfff00000) == TXX9_CE(1)) IO_BASE 448 arch/mips/txx9/rbtx4939/setup.c unsigned long smc_addr = RBTX4939_ETHER_ADDR - IO_BASE; IO_BASE 1248 drivers/pci/hotplug/cpqphp_pci.c u16 io_base = readw(one_slot + IO_BASE); IO_BASE 132 drivers/video/fbdev/dnfb.c .smem_start = (FRAME_BUFFER_START + IO_BASE), IO_BASE 92 drivers/watchdog/sb_wdog.c static char __iomem *kern_dog = (char __iomem *)(IO_BASE + (A_SCD_WDOG_CFG_0)); IO_BASE 93 drivers/watchdog/sb_wdog.c static char __iomem *user_dog = (char __iomem *)(IO_BASE + (A_SCD_WDOG_CFG_1));