IOMEM 5 arch/arm/include/asm/v7m.h #define V7M_SCS_ICTR IOMEM(0xe000e004) IOMEM 8 arch/arm/include/asm/v7m.h #define BASEADDR_V7M_SCB IOMEM(0xe000ed00) IOMEM 19 arch/arm/mach-clps711x/board-dt.c #define CLPS711X_VIRT_BASE IOMEM(0xfeff4000) IOMEM 90 arch/arm/mach-cns3xxx/core.c gic_init(IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), IOMEM 91 arch/arm/mach-cns3xxx/core.c IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT)); IOMEM 96 arch/arm/mach-cns3xxx/core.c u32 __iomem *pm_base = IOMEM(CNS3XXX_PM_BASE_VIRT); IOMEM 255 arch/arm/mach-cns3xxx/core.c cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT); IOMEM 382 arch/arm/mach-cns3xxx/core.c u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014); IOMEM 97 arch/arm/mach-cns3xxx/devices.c u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014); IOMEM 31 arch/arm/mach-davinci/include/mach/hardware.h #define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa)) IOMEM 28 arch/arm/mach-dove/dove.h #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000) IOMEM 41 arch/arm/mach-dove/dove.h #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000) IOMEM 45 arch/arm/mach-dove/dove.h #define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfec00000) IOMEM 49 arch/arm/mach-dove/dove.h #define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe400000) IOMEM 31 arch/arm/mach-ebsa110/core.h #define PIT_BASE IOMEM(0xfc000000) /* trick 0 */ IOMEM 32 arch/arm/mach-ebsa110/core.h #define SOFT_BASE IOMEM(0xfd000000) /* trick 1 */ IOMEM 33 arch/arm/mach-ebsa110/core.h #define IRQ_MASK IOMEM(0xfe000000) /* trick 3 - read */ IOMEM 34 arch/arm/mach-ebsa110/core.h #define IRQ_MSET IOMEM(0xfe000000) /* trick 3 - write */ IOMEM 35 arch/arm/mach-ebsa110/core.h #define IRQ_STAT IOMEM(0xff000000) /* trick 4 - read */ IOMEM 36 arch/arm/mach-ebsa110/core.h #define IRQ_MCLR IOMEM(0xff000000) /* trick 4 - write */ IOMEM 23 arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h #define EP93XX_AHB_IOMEM(x) IOMEM(EP93XX_AHB_VIRT_BASE + (x)) IOMEM 30 arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h #define EP93XX_APB_IOMEM(x) IOMEM(EP93XX_APB_VIRT_BASE + (x)) IOMEM 20 arch/arm/mach-ep93xx/ts72xx.h #define TS72XX_MODEL_VIRT_BASE IOMEM(0xfebff000) IOMEM 32 arch/arm/mach-ep93xx/ts72xx.h #define TS72XX_OPTIONS_VIRT_BASE IOMEM(0xfebfe000) IOMEM 40 arch/arm/mach-ep93xx/ts72xx.h #define TS72XX_OPTIONS2_VIRT_BASE IOMEM(0xfebfd000) IOMEM 47 arch/arm/mach-ep93xx/ts72xx.h #define TS72XX_CPLDVER_VIRT_BASE IOMEM(0xfebfc000) IOMEM 92 arch/arm/mach-imx/hardware.h #define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x)) IOMEM 35 arch/arm/mach-imx/mach-kzm_arm11_01.c #define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \ IOMEM 86 arch/arm/mach-imx/mx21.h #define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x)) IOMEM 115 arch/arm/mach-imx/mx27.h #define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) IOMEM 80 arch/arm/mach-imx/mx31.h #define MX31_ROMP_BASE_ADDR_VIRT IOMEM(0xfc500000) IOMEM 96 arch/arm/mach-imx/mx31.h #define MX31_CS4_BASE_ADDR_VIRT IOMEM(0xf6000000) IOMEM 100 arch/arm/mach-imx/mx31.h #define MX31_CS5_BASE_ADDR_VIRT IOMEM(0xf8000000) IOMEM 120 arch/arm/mach-imx/mx31.h #define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x)) IOMEM 119 arch/arm/mach-imx/mx35.h #define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x)) IOMEM 181 arch/arm/mach-iop32x/glantank.c __raw_writeb(0x01, IOMEM(0xfe8d0004)); IOMEM 48 arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h #define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000) IOMEM 55 arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h #define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEF13000) IOMEM 711 arch/arm/mach-lpc32xx/lpc32xx.h #define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ IOMEM 16 arch/arm/mach-mmp/addr-map.h #define APB_VIRT_BASE IOMEM(0xfe000000) IOMEM 20 arch/arm/mach-mmp/addr-map.h #define AXI_VIRT_BASE IOMEM(0xfe200000) IOMEM 44 arch/arm/mach-mv78xx0/mv78xx0.h #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000) IOMEM 52 arch/arm/mach-mv78xx0/mv78xx0.h #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000) IOMEM 791 arch/arm/mach-omap1/board-ams-delta.c .membase = IOMEM(MODEM_VIRT), IOMEM 28 arch/arm/mach-omap1/fpga.h #define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ IOMEM 29 arch/arm/mach-omap1/fpga.h #define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */ IOMEM 30 arch/arm/mach-omap1/fpga.h #define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */ IOMEM 31 arch/arm/mach-omap1/fpga.h #define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */ IOMEM 32 arch/arm/mach-omap1/fpga.h #define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */ IOMEM 33 arch/arm/mach-omap1/fpga.h #define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */ IOMEM 34 arch/arm/mach-omap1/fpga.h #define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */ IOMEM 76 arch/arm/mach-omap1/include/mach/hardware.h #define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET) IOMEM 126 arch/arm/mach-omap1/include/mach/hardware.h #define DSP_CONFIG_REG_BASE IOMEM(0xe1008000) IOMEM 58 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0) IOMEM 59 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1) IOMEM 60 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510_FPGA_LCD_PANEL_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x2) IOMEM 61 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510_FPGA_LED_DIGIT IOMEM(OMAP1510_FPGA_BASE + 0x3) IOMEM 62 arch/arm/mach-omap1/include/mach/omap1510.h #define INNOVATOR_FPGA_HID_SPI IOMEM(OMAP1510_FPGA_BASE + 0x4) IOMEM 63 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510_FPGA_POWER IOMEM(OMAP1510_FPGA_BASE + 0x5) IOMEM 66 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510_FPGA_ISR_LO IOMEM(OMAP1510_FPGA_BASE + 0x6) IOMEM 67 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510_FPGA_ISR_HI IOMEM(OMAP1510_FPGA_BASE + 0x7) IOMEM 70 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510_FPGA_IMR_LO IOMEM(OMAP1510_FPGA_BASE + 0x8) IOMEM 71 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510_FPGA_IMR_HI IOMEM(OMAP1510_FPGA_BASE + 0x9) IOMEM 74 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510_FPGA_HOST_RESET IOMEM(OMAP1510_FPGA_BASE + 0xa) IOMEM 75 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510_FPGA_RST IOMEM(OMAP1510_FPGA_BASE + 0xb) IOMEM 77 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510_FPGA_AUDIO IOMEM(OMAP1510_FPGA_BASE + 0xc) IOMEM 78 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510_FPGA_DIP IOMEM(OMAP1510_FPGA_BASE + 0xe) IOMEM 79 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510_FPGA_FPGA_IO IOMEM(OMAP1510_FPGA_BASE + 0xf) IOMEM 80 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510_FPGA_UART1 IOMEM(OMAP1510_FPGA_BASE + 0x14) IOMEM 81 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510_FPGA_UART2 IOMEM(OMAP1510_FPGA_BASE + 0x15) IOMEM 82 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510_FPGA_OMAP1510_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x16) IOMEM 83 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510_FPGA_BOARD_REV IOMEM(OMAP1510_FPGA_BASE + 0x18) IOMEM 84 arch/arm/mach-omap1/include/mach/omap1510.h #define INNOVATOR_FPGA_CAM_USB_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20c) IOMEM 85 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510P1_PPT_DATA IOMEM(OMAP1510_FPGA_BASE + 0x100) IOMEM 86 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510P1_PPT_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x101) IOMEM 87 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510P1_PPT_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x102) IOMEM 89 arch/arm/mach-omap1/include/mach/omap1510.h #define OMAP1510_FPGA_TOUCHSCREEN IOMEM(OMAP1510_FPGA_BASE + 0x204) IOMEM 91 arch/arm/mach-omap1/include/mach/omap1510.h #define INNOVATOR_FPGA_INFO IOMEM(OMAP1510_FPGA_BASE + 0x205) IOMEM 92 arch/arm/mach-omap1/include/mach/omap1510.h #define INNOVATOR_FPGA_LCD_BRIGHT_LO IOMEM(OMAP1510_FPGA_BASE + 0x206) IOMEM 93 arch/arm/mach-omap1/include/mach/omap1510.h #define INNOVATOR_FPGA_LCD_BRIGHT_HI IOMEM(OMAP1510_FPGA_BASE + 0x207) IOMEM 94 arch/arm/mach-omap1/include/mach/omap1510.h #define INNOVATOR_FPGA_LED_GRN_LO IOMEM(OMAP1510_FPGA_BASE + 0x208) IOMEM 95 arch/arm/mach-omap1/include/mach/omap1510.h #define INNOVATOR_FPGA_LED_GRN_HI IOMEM(OMAP1510_FPGA_BASE + 0x209) IOMEM 96 arch/arm/mach-omap1/include/mach/omap1510.h #define INNOVATOR_FPGA_LED_RED_LO IOMEM(OMAP1510_FPGA_BASE + 0x20a) IOMEM 97 arch/arm/mach-omap1/include/mach/omap1510.h #define INNOVATOR_FPGA_LED_RED_HI IOMEM(OMAP1510_FPGA_BASE + 0x20b) IOMEM 98 arch/arm/mach-omap1/include/mach/omap1510.h #define INNOVATOR_FPGA_EXP_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20d) IOMEM 99 arch/arm/mach-omap1/include/mach/omap1510.h #define INNOVATOR_FPGA_ISR2 IOMEM(OMAP1510_FPGA_BASE + 0x20e) IOMEM 100 arch/arm/mach-omap1/include/mach/omap1510.h #define INNOVATOR_FPGA_IMR2 IOMEM(OMAP1510_FPGA_BASE + 0x210) IOMEM 34 arch/arm/mach-omap2/iomap.h #define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */ IOMEM 37 arch/arm/mach-omap2/iomap.h #define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */ IOMEM 40 arch/arm/mach-omap2/iomap.h #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */ IOMEM 43 arch/arm/mach-omap2/iomap.h #define AM33XX_L4_WK_IO_ADDRESS(pa) IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET) IOMEM 46 arch/arm/mach-omap2/iomap.h #define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET) IOMEM 49 arch/arm/mach-omap2/iomap.h #define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET) IOMEM 40 arch/arm/mach-orion5x/orion5x.h #define ORION5X_REGS_VIRT_BASE IOMEM(0xfec00000) IOMEM 56 arch/arm/mach-orion5x/orion5x.h #define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000) IOMEM 37 arch/arm/mach-orion5x/ts78xx-setup.c #define TS78XX_FPGA_REGS_VIRT_BASE IOMEM(0xff900000) IOMEM 24 arch/arm/mach-pxa/include/mach/addr-map.h #define PERIPH_VIRT IOMEM(0xf2000000) IOMEM 32 arch/arm/mach-pxa/include/mach/addr-map.h #define SMEMC_VIRT IOMEM(0xf6000000) IOMEM 39 arch/arm/mach-pxa/include/mach/addr-map.h #define DMEMC_VIRT IOMEM(0xf6100000) IOMEM 51 arch/arm/mach-pxa/include/mach/addr-map.h #define NAND_VIRT IOMEM(0xf6300000) IOMEM 58 arch/arm/mach-pxa/include/mach/addr-map.h #define IMEMC_VIRT IOMEM(0xfe000000) IOMEM 25 arch/arm/mach-pxa/include/mach/balloon3.h #define BALLOON3_FPGA_VIRT IOMEM(0xf1000000) /* as per balloon2 */ IOMEM 37 arch/arm/mach-pxa/include/mach/hardware.h #define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) IOMEM 72 arch/arm/mach-pxa/include/mach/palmtx.h #define PALMTX_PCMCIA_VIRT IOMEM(0xf0000000) IOMEM 85 arch/arm/mach-pxa/include/mach/palmtx.h #define PALMTX_NAND_ALE_VIRT IOMEM(0xff100000) IOMEM 86 arch/arm/mach-pxa/include/mach/palmtx.h #define PALMTX_NAND_CLE_VIRT IOMEM(0xff200000) IOMEM 13 arch/arm/mach-pxa/include/mach/smemc.h #define SMEMC_VIRT IOMEM(0xf6000000) IOMEM 13 arch/arm/mach-pxa/lpd270.h #define LPD270_CPLD_VIRT IOMEM(0xf0000000) IOMEM 68 arch/arm/mach-pxa/zeus.h #define ZEUS_CPLD IOMEM(0xf0000000) IOMEM 76 arch/arm/mach-pxa/zeus.h #define ZEUS_PC104IO IOMEM(0xf1000000) IOMEM 30 arch/arm/mach-rpc/include/mach/hardware.h #define EASI_BASE IOMEM(0xe5000000) IOMEM 34 arch/arm/mach-rpc/include/mach/hardware.h #define IO_BASE IOMEM(0xe0000000) IOMEM 36 arch/arm/mach-sa1100/include/mach/hardware.h IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE ) IOMEM 40 arch/arm/mach-sa1100/include/mach/hardware.h #define __MREG(x) IOMEM(io_p2v(x)) IOMEM 91 arch/arm/mach-sa1100/include/mach/simpad.h #define CS3_BASE IOMEM(0xf1000000) IOMEM 42 arch/arm/mach-shmobile/setup-r8a7779.c #define INT2SMSKCR0 IOMEM(0xfe7822a0) IOMEM 43 arch/arm/mach-shmobile/setup-r8a7779.c #define INT2SMSKCR1 IOMEM(0xfe7822a4) IOMEM 44 arch/arm/mach-shmobile/setup-r8a7779.c #define INT2SMSKCR2 IOMEM(0xfe7822a8) IOMEM 45 arch/arm/mach-shmobile/setup-r8a7779.c #define INT2SMSKCR3 IOMEM(0xfe7822ac) IOMEM 46 arch/arm/mach-shmobile/setup-r8a7779.c #define INT2SMSKCR4 IOMEM(0xfe7822b0) IOMEM 48 arch/arm/mach-shmobile/setup-r8a7779.c #define INT2NTSR0 IOMEM(0xfe700060) IOMEM 49 arch/arm/mach-shmobile/setup-r8a7779.c #define INT2NTSR1 IOMEM(0xfe700064) IOMEM 47 arch/arm/mach-shmobile/setup-sh73a0.c l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff); IOMEM 23 arch/arm/mach-shmobile/smp-r8a7779.c #define AVECR IOMEM(0xfe700040) IOMEM 19 arch/arm/mach-shmobile/smp-sh73a0.c #define WUPCR IOMEM(0xe6151010) IOMEM 20 arch/arm/mach-shmobile/smp-sh73a0.c #define SRESCR IOMEM(0xe6151018) IOMEM 21 arch/arm/mach-shmobile/smp-sh73a0.c #define PSTR IOMEM(0xe6151040) IOMEM 22 arch/arm/mach-shmobile/smp-sh73a0.c #define SBAR IOMEM(0xe6180020) IOMEM 23 arch/arm/mach-shmobile/smp-sh73a0.c #define APARMBAREA IOMEM(0xe6f10020) IOMEM 22 arch/arm/mach-spear/include/mach/spear.h #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000) IOMEM 29 arch/arm/mach-spear/include/mach/spear.h #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000) IOMEM 33 arch/arm/mach-spear/include/mach/spear.h #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000) IOMEM 50 arch/arm/mach-spear/include/mach/spear.h #define VA_SPEAR320_SOC_CONFIG_BASE IOMEM(0xFE000000) IOMEM 55 arch/arm/mach-spear/include/mach/spear.h #define VA_PERIP_GRP2_BASE IOMEM(0xF9000000) IOMEM 58 arch/arm/mach-spear/include/mach/spear.h #define VA_SYSRAM0_BASE IOMEM(0xF9800000) IOMEM 62 arch/arm/mach-spear/include/mach/spear.h #define VA_PERIP_GRP1_BASE IOMEM(0xFD000000) IOMEM 64 arch/arm/mach-spear/include/mach/spear.h #define VA_UART_BASE IOMEM(0xFD000000) IOMEM 67 arch/arm/mach-spear/include/mach/spear.h #define VA_MISC_BASE IOMEM(0xFD700000) IOMEM 70 arch/arm/mach-spear/include/mach/spear.h #define VA_A9SM_AND_MPMC_BASE IOMEM(0xFC000000) IOMEM 73 arch/arm/mach-spear/include/mach/spear.h #define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000)) IOMEM 77 arch/arm/mach-spear/include/mach/spear.h #define VA_A9SM_PERIP_BASE IOMEM(0xFC800000) IOMEM 81 arch/arm/mach-spear/include/mach/spear.h #define VA_L2CC_BASE IOMEM(UL(0xFB000000)) IOMEM 39 arch/arm/mach-spear/platsmp.c static void __iomem *scu_base = IOMEM(VA_SCU_BASE); IOMEM 98 arch/arm/mach-tegra/iomap.h #define IO_IRAM_VIRT IOMEM(0xFE400000) IOMEM 102 arch/arm/mach-tegra/iomap.h #define IO_CPU_VIRT IOMEM(0xFE440000) IOMEM 106 arch/arm/mach-tegra/iomap.h #define IO_PPSB_VIRT IOMEM(0xFE200000) IOMEM 110 arch/arm/mach-tegra/iomap.h #define IO_APB_VIRT IOMEM(0xFE000000) IOMEM 58 arch/arm/mach-u300/core.c #define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000) IOMEM 61 arch/arm/mach-u300/core.c #define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000) IOMEM 96 arch/arm/mach-u300/core.c #define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000) IOMEM 103 arch/arm/mach-u300/core.c #define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000) IOMEM 181 arch/arm/mach-ux500/db8500-regs.h #define UX500_VIRT_ROM IOMEM(0xf0000000) IOMEM 188 arch/arm/mach-ux500/db8500-regs.h #define __io_address(n) IOMEM(IO_ADDRESS(n)) IOMEM 56 arch/arm/plat-omap/sram.c omap_sram_ceil = IOMEM(new_ceil); IOMEM 296 arch/mips/alchemy/common/clock.c void __iomem *addr = IOMEM(AU1000_MEM_PHYS_ADDR); IOMEM 64 drivers/gpio/gpio-zevio.c return readl(IOMEM(c->chip.regs + section_offset + port_offset)); IOMEM 71 drivers/gpio/gpio-zevio.c writel(val, IOMEM(c->chip.regs + section_offset + port_offset)); IOMEM 42 drivers/input/mouse/rpcmouse.c b = (short) (__raw_readl(IOMEM(0xe0310000)) ^ 0x70);