IOADDR 36 arch/mips/kernel/cevt-bcm1480.c cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); IOADDR 37 arch/mips/kernel/cevt-bcm1480.c init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); IOADDR 50 arch/mips/kernel/cevt-bcm1480.c cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); IOADDR 62 arch/mips/kernel/cevt-bcm1480.c cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); IOADDR 63 arch/mips/kernel/cevt-bcm1480.c init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); IOADDR 85 arch/mips/kernel/cevt-bcm1480.c cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); IOADDR 131 arch/mips/kernel/cevt-bcm1480.c IOADDR(A_BCM1480_IMR_REGISTER(cpu, IOADDR 33 arch/mips/kernel/cevt-sb1250.c cfg = IOADDR(A_SCD_TIMER_REGISTER(smp_processor_id(), R_SCD_TIMER_CFG)); IOADDR 46 arch/mips/kernel/cevt-sb1250.c cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); IOADDR 47 arch/mips/kernel/cevt-sb1250.c init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); IOADDR 61 arch/mips/kernel/cevt-sb1250.c cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); IOADDR 62 arch/mips/kernel/cevt-sb1250.c init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); IOADDR 84 arch/mips/kernel/cevt-sb1250.c cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); IOADDR 131 arch/mips/kernel/cevt-sb1250.c IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + IOADDR 21 arch/mips/kernel/csrc-bcm1480.c return (u64) __raw_readq(IOADDR(A_SCD_ZBBUS_CYCLE_COUNT)); IOADDR 34 arch/mips/kernel/csrc-bcm1480.c return __raw_readq(IOADDR(A_SCD_ZBBUS_CYCLE_COUNT)); IOADDR 43 arch/mips/kernel/csrc-bcm1480.c plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG))); IOADDR 29 arch/mips/kernel/csrc-sb1250.c addr = IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT)); IOADDR 59 arch/mips/kernel/csrc-sb1250.c IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, IOADDR 62 arch/mips/kernel/csrc-sb1250.c IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, IOADDR 65 arch/mips/kernel/csrc-sb1250.c IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, IOADDR 139 arch/mips/mm/cerr-sb1.c status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); IOADDR 142 arch/mips/mm/cerr-sb1.c l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS)); IOADDR 144 arch/mips/mm/cerr-sb1.c l2_tag = in64(IOADDR(A_L2_ECC_TAG)); IOADDR 146 arch/mips/mm/cerr-sb1.c memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); IOADDR 172 arch/mips/mm/cerr-sb1.c csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG)); IOADDR 638 arch/mips/mm/page.c __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); IOADDR 644 arch/mips/mm/page.c while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG))) IOADDR 647 arch/mips/mm/page.c __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); IOADDR 665 arch/mips/mm/page.c __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); IOADDR 671 arch/mips/mm/page.c while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG))) IOADDR 674 arch/mips/mm/page.c __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); IOADDR 210 arch/mips/pci/pci-bcm1480.c reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG)); IOADDR 219 arch/mips/pci/pci-sb1250.c reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG)); IOADDR 53 arch/mips/sibyte/bcm1480/irq.c cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); IOADDR 55 arch/mips/sibyte/bcm1480/irq.c ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); IOADDR 70 arch/mips/sibyte/bcm1480/irq.c cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); IOADDR 72 arch/mips/sibyte/bcm1480/irq.c ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); IOADDR 101 arch/mips/sibyte/bcm1480/irq.c cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); IOADDR 106 arch/mips/sibyte/bcm1480/irq.c ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); IOADDR 111 arch/mips/sibyte/bcm1480/irq.c cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); IOADDR 113 arch/mips/sibyte/bcm1480/irq.c ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); IOADDR 157 arch/mips/sibyte/bcm1480/irq.c pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq], IOADDR 168 arch/mips/sibyte/bcm1480/irq.c __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i), IOADDR 172 arch/mips/sibyte/bcm1480/irq.c __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING)))); IOADDR 249 arch/mips/sibyte/bcm1480/irq.c IOADDR(A_BCM1480_IMR_REGISTER(cpu, IOADDR 258 arch/mips/sibyte/bcm1480/irq.c IOADDR(A_BCM1480_IMR_REGISTER(cpu, IOADDR 271 arch/mips/sibyte/bcm1480/irq.c __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + IOADDR 279 arch/mips/sibyte/bcm1480/irq.c IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU))); IOADDR 281 arch/mips/sibyte/bcm1480/irq.c IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU))); IOADDR 288 arch/mips/sibyte/bcm1480/irq.c __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H))); IOADDR 292 arch/mips/sibyte/bcm1480/irq.c __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L))); IOADDR 320 arch/mips/sibyte/bcm1480/irq.c IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H)); IOADDR 322 arch/mips/sibyte/bcm1480/irq.c IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L)); IOADDR 112 arch/mips/sibyte/bcm1480/setup.c sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION)); IOADDR 122 arch/mips/sibyte/bcm1480/setup.c plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG))); IOADDR 26 arch/mips/sibyte/bcm1480/smp.c IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), IOADDR 27 arch/mips/sibyte/bcm1480/smp.c IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), IOADDR 28 arch/mips/sibyte/bcm1480/smp.c IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), IOADDR 29 arch/mips/sibyte/bcm1480/smp.c IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), IOADDR 33 arch/mips/sibyte/bcm1480/smp.c IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), IOADDR 34 arch/mips/sibyte/bcm1480/smp.c IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), IOADDR 35 arch/mips/sibyte/bcm1480/smp.c IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), IOADDR 36 arch/mips/sibyte/bcm1480/smp.c IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), IOADDR 40 arch/mips/sibyte/bcm1480/smp.c IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), IOADDR 41 arch/mips/sibyte/bcm1480/smp.c IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), IOADDR 42 arch/mips/sibyte/bcm1480/smp.c IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), IOADDR 43 arch/mips/sibyte/bcm1480/smp.c IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), IOADDR 73 arch/mips/sibyte/common/bus_watcher.c status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG)); IOADDR 77 arch/mips/sibyte/common/bus_watcher.c status = csr_in32(IOADDR(A_BCM1480_BUS_ERR_STATUS_DEBUG)); IOADDR 87 arch/mips/sibyte/common/bus_watcher.c l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS)); IOADDR 88 arch/mips/sibyte/common/bus_watcher.c memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); IOADDR 161 arch/mips/sibyte/common/bus_watcher.c csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG)); IOADDR 162 arch/mips/sibyte/common/bus_watcher.c csr_out32(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG)); IOADDR 166 arch/mips/sibyte/common/bus_watcher.c (long long)__raw_readq(IOADDR(A_SCD_TRACE_READ))); IOADDR 168 arch/mips/sibyte/common/bus_watcher.c csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); IOADDR 169 arch/mips/sibyte/common/bus_watcher.c csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG)); IOADDR 173 arch/mips/sibyte/common/bus_watcher.c stats->status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); IOADDR 176 arch/mips/sibyte/common/bus_watcher.c stats->l2_err = cntr = csr_in32(IOADDR(A_BUS_L2_ERRORS)); IOADDR 181 arch/mips/sibyte/common/bus_watcher.c csr_out32(0, IOADDR(A_BUS_L2_ERRORS)); IOADDR 183 arch/mips/sibyte/common/bus_watcher.c stats->memio_err = cntr = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); IOADDR 187 arch/mips/sibyte/common/bus_watcher.c csr_out32(0, IOADDR(A_BUS_MEM_IO_ERRORS)); IOADDR 220 arch/mips/sibyte/common/bus_watcher.c IOADDR(A_SCD_TRACE_SEQUENCE_0)); IOADDR 221 arch/mips/sibyte/common/bus_watcher.c csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); IOADDR 222 arch/mips/sibyte/common/bus_watcher.c csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG)); IOADDR 152 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1)); IOADDR 153 arch/mips/sibyte/common/sb_tbprof.c scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG)); IOADDR 164 arch/mips/sibyte/common/sb_tbprof.c IOADDR(A_BCM1480_SCD_PERF_CNT_CFG0)); IOADDR 169 arch/mips/sibyte/common/sb_tbprof.c IOADDR(A_BCM1480_SCD_PERF_CNT_CFG1)); IOADDR 176 arch/mips/sibyte/common/sb_tbprof.c IOADDR(A_SCD_PERF_CNT_CFG)); IOADDR 178 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1)); IOADDR 180 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); IOADDR 185 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG)); IOADDR 200 arch/mips/sibyte/common/sb_tbprof.c IOADDR(A_SCD_TRACE_CFG)); IOADDR 206 arch/mips/sibyte/common/sb_tbprof.c p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); IOADDR 208 arch/mips/sibyte/common/sb_tbprof.c p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); IOADDR 210 arch/mips/sibyte/common/sb_tbprof.c p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); IOADDR 212 arch/mips/sibyte/common/sb_tbprof.c p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); IOADDR 214 arch/mips/sibyte/common/sb_tbprof.c p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); IOADDR 216 arch/mips/sibyte/common/sb_tbprof.c p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); IOADDR 222 arch/mips/sibyte/common/sb_tbprof.c IOADDR(A_SCD_TRACE_CFG)); IOADDR 232 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); IOADDR 272 arch/mips/sibyte/common/sb_tbprof.c scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG)); IOADDR 276 arch/mips/sibyte/common/sb_tbprof.c IOADDR(A_SCD_PERF_CNT_CFG)); IOADDR 295 arch/mips/sibyte/common/sb_tbprof.c IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + IOADDR 299 arch/mips/sibyte/common/sb_tbprof.c IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + IOADDR 304 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0)); IOADDR 305 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1)); IOADDR 306 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2)); IOADDR 307 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3)); IOADDR 309 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0)); IOADDR 310 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1)); IOADDR 311 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2)); IOADDR 312 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3)); IOADDR 314 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0)); IOADDR 315 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1)); IOADDR 316 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2)); IOADDR 317 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3)); IOADDR 321 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0)); IOADDR 322 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1)); IOADDR 323 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2)); IOADDR 324 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3)); IOADDR 325 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4)); IOADDR 326 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5)); IOADDR 327 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6)); IOADDR 328 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7)); IOADDR 333 arch/mips/sibyte/common/sb_tbprof.c IOADDR(A_SCD_TRACE_SEQUENCE_0)); IOADDR 337 arch/mips/sibyte/common/sb_tbprof.c IOADDR(A_SCD_TRACE_SEQUENCE_1)); IOADDR 338 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2)); IOADDR 339 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3)); IOADDR 340 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4)); IOADDR 341 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5)); IOADDR 342 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6)); IOADDR 343 arch/mips/sibyte/common/sb_tbprof.c __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7)); IOADDR 348 arch/mips/sibyte/common/sb_tbprof.c IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_TRACE_L))); IOADDR 351 arch/mips/sibyte/common/sb_tbprof.c IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE))); IOADDR 47 arch/mips/sibyte/sb1250/irq.c cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + IOADDR 50 arch/mips/sibyte/sb1250/irq.c ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + IOADDR 61 arch/mips/sibyte/sb1250/irq.c cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + IOADDR 64 arch/mips/sibyte/sb1250/irq.c ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + IOADDR 88 arch/mips/sibyte/sb1250/irq.c cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) + IOADDR 94 arch/mips/sibyte/sb1250/irq.c ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) + IOADDR 100 arch/mips/sibyte/sb1250/irq.c cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + IOADDR 103 arch/mips/sibyte/sb1250/irq.c ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + IOADDR 139 arch/mips/sibyte/sb1250/irq.c pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq], IOADDR 156 arch/mips/sibyte/sb1250/irq.c IOADDR(A_IMR_REGISTER(cpu, IOADDR 231 arch/mips/sibyte/sb1250/irq.c IOADDR(A_IMR_REGISTER(0, IOADDR 235 arch/mips/sibyte/sb1250/irq.c IOADDR(A_IMR_REGISTER(1, IOADDR 248 arch/mips/sibyte/sb1250/irq.c IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + IOADDR 251 arch/mips/sibyte/sb1250/irq.c IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + IOADDR 256 arch/mips/sibyte/sb1250/irq.c IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); IOADDR 258 arch/mips/sibyte/sb1250/irq.c IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); IOADDR 262 arch/mips/sibyte/sb1250/irq.c __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); IOADDR 263 arch/mips/sibyte/sb1250/irq.c __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); IOADDR 287 arch/mips/sibyte/sb1250/irq.c mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu, IOADDR 175 arch/mips/sibyte/sb1250/setup.c sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION)); IOADDR 184 arch/mips/sibyte/sb1250/setup.c plldiv = G_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG))); IOADDR 21 arch/mips/sibyte/sb1250/smp.c IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU), IOADDR 22 arch/mips/sibyte/sb1250/smp.c IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU) IOADDR 26 arch/mips/sibyte/sb1250/smp.c IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU), IOADDR 27 arch/mips/sibyte/sb1250/smp.c IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU) IOADDR 31 arch/mips/sibyte/sb1250/smp.c IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU), IOADDR 32 arch/mips/sibyte/sb1250/smp.c IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU) IOADDR 81 arch/mips/sibyte/swarm/rtc_m41t81.c #define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg)) IOADDR 56 arch/mips/sibyte/swarm/rtc_xicor1241.c #define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg)) IOADDR 162 arch/mips/sibyte/swarm/setup.c reg = IOADDR(LEDS_PHYS) + 0x20 + ((3 - i) << 3); IOADDR 25 arch/xtensa/platforms/xt2000/include/platform/hardware.h #define SONIC83934_ADDR IOADDR(0x0d030000) IOADDR 41 arch/xtensa/platforms/xt2000/include/platform/hardware.h #define XT2000_LED_ADDR IOADDR(0x0d040000) IOADDR 22 arch/xtensa/platforms/xt2000/include/platform/serial.h #define DUART16552_1_ADDR IOADDR(0x0d050020) /* channel 1 */ IOADDR 23 arch/xtensa/platforms/xt2000/include/platform/serial.h #define DUART16552_2_ADDR IOADDR(0x0d050000) /* channel 2 */ IOADDR 40 arch/xtensa/platforms/xtfpga/include/platform/hardware.h #define XTFPGA_FPGAREGS_VADDR IOADDR(0x0D020000) IOADDR 21 arch/xtensa/platforms/xtfpga/lcd.c #define LCD_INSTR_ADDR ((char *)IOADDR(CONFIG_XTFPGA_LCD_BASE_ADDR))