INTERRUPT_BASE     46 drivers/media/pci/ddbridge/ddbridge-regs.h #define INTERRUPT_ENABLE (INTERRUPT_BASE + 0x00)
INTERRUPT_BASE     47 drivers/media/pci/ddbridge/ddbridge-regs.h #define MSI1_ENABLE      (INTERRUPT_BASE + 0x04)
INTERRUPT_BASE     48 drivers/media/pci/ddbridge/ddbridge-regs.h #define MSI2_ENABLE      (INTERRUPT_BASE + 0x08)
INTERRUPT_BASE     49 drivers/media/pci/ddbridge/ddbridge-regs.h #define MSI3_ENABLE      (INTERRUPT_BASE + 0x0C)
INTERRUPT_BASE     50 drivers/media/pci/ddbridge/ddbridge-regs.h #define MSI4_ENABLE      (INTERRUPT_BASE + 0x10)
INTERRUPT_BASE     51 drivers/media/pci/ddbridge/ddbridge-regs.h #define MSI5_ENABLE      (INTERRUPT_BASE + 0x14)
INTERRUPT_BASE     52 drivers/media/pci/ddbridge/ddbridge-regs.h #define MSI6_ENABLE      (INTERRUPT_BASE + 0x18)
INTERRUPT_BASE     53 drivers/media/pci/ddbridge/ddbridge-regs.h #define MSI7_ENABLE      (INTERRUPT_BASE + 0x1C)
INTERRUPT_BASE     55 drivers/media/pci/ddbridge/ddbridge-regs.h #define INTERRUPT_STATUS (INTERRUPT_BASE + 0x20)
INTERRUPT_BASE     56 drivers/media/pci/ddbridge/ddbridge-regs.h #define INTERRUPT_ACK    (INTERRUPT_BASE + 0x20)