INTEL_GVT_IRQ_INFO_GT0  303 drivers/gpu/drm/i915/gvt/interrupt.c 	{ INTEL_GVT_IRQ_INFO_MASTER, 0, INTEL_GVT_IRQ_INFO_GT0, 0xffff },
INTEL_GVT_IRQ_INFO_GT0  304 drivers/gpu/drm/i915/gvt/interrupt.c 	{ INTEL_GVT_IRQ_INFO_MASTER, 1, INTEL_GVT_IRQ_INFO_GT0, 0xffff0000 },
INTEL_GVT_IRQ_INFO_GT0  511 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT0, &gen8_gt0_info);
INTEL_GVT_IRQ_INFO_GT0  526 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 0, RCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);
INTEL_GVT_IRQ_INFO_GT0  527 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 4, RCS_PIPE_CONTROL, INTEL_GVT_IRQ_INFO_GT0);
INTEL_GVT_IRQ_INFO_GT0  528 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 8, RCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);
INTEL_GVT_IRQ_INFO_GT0  530 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 16, BCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);
INTEL_GVT_IRQ_INFO_GT0  531 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 20, BCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT0);
INTEL_GVT_IRQ_INFO_GT0  532 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 24, BCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);