INTEL_GVT_IRQ_INFO_DE_PIPE_B  310 drivers/gpu/drm/i915/gvt/interrupt.c 	{ INTEL_GVT_IRQ_INFO_MASTER, 17, INTEL_GVT_IRQ_INFO_DE_PIPE_B, ~0 },
INTEL_GVT_IRQ_INFO_DE_PIPE_B  516 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_B, &gen8_de_pipe_b_info);
INTEL_GVT_IRQ_INFO_DE_PIPE_B  554 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 0, PIPE_B_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
INTEL_GVT_IRQ_INFO_DE_PIPE_B  579 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 4, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
INTEL_GVT_IRQ_INFO_DE_PIPE_B  580 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 5, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
INTEL_GVT_IRQ_INFO_DE_PIPE_B  590 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 3, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
INTEL_GVT_IRQ_INFO_DE_PIPE_B  594 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 4, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);