INTEL_GVT_IRQ_INFO_DE_PIPE_A  309 drivers/gpu/drm/i915/gvt/interrupt.c 	{ INTEL_GVT_IRQ_INFO_MASTER, 16, INTEL_GVT_IRQ_INFO_DE_PIPE_A, ~0 },
INTEL_GVT_IRQ_INFO_DE_PIPE_A  515 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_A, &gen8_de_pipe_a_info);
INTEL_GVT_IRQ_INFO_DE_PIPE_A  553 drivers/gpu/drm/i915/gvt/interrupt.c 	SET_BIT_INFO(irq, 0, PIPE_A_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
INTEL_GVT_IRQ_INFO_DE_PIPE_A  576 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 4, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
INTEL_GVT_IRQ_INFO_DE_PIPE_A  577 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 5, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
INTEL_GVT_IRQ_INFO_DE_PIPE_A  589 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 3, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
INTEL_GVT_IRQ_INFO_DE_PIPE_A  593 drivers/gpu/drm/i915/gvt/interrupt.c 		SET_BIT_INFO(irq, 4, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);