INTEL_EVENT_CONSTRAINT 44 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ INTEL_EVENT_CONSTRAINT 45 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ INTEL_EVENT_CONSTRAINT 46 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ INTEL_EVENT_CONSTRAINT 47 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ INTEL_EVENT_CONSTRAINT 48 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ INTEL_EVENT_CONSTRAINT 49 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ INTEL_EVENT_CONSTRAINT 58 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ INTEL_EVENT_CONSTRAINT 59 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ INTEL_EVENT_CONSTRAINT 60 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ INTEL_EVENT_CONSTRAINT 61 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ INTEL_EVENT_CONSTRAINT 62 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ INTEL_EVENT_CONSTRAINT 63 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ INTEL_EVENT_CONSTRAINT 64 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ INTEL_EVENT_CONSTRAINT 65 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ INTEL_EVENT_CONSTRAINT 66 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ INTEL_EVENT_CONSTRAINT 67 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ INTEL_EVENT_CONSTRAINT 76 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ INTEL_EVENT_CONSTRAINT 77 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ INTEL_EVENT_CONSTRAINT 78 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ INTEL_EVENT_CONSTRAINT 79 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ INTEL_EVENT_CONSTRAINT 80 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ INTEL_EVENT_CONSTRAINT 81 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ INTEL_EVENT_CONSTRAINT 82 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ INTEL_EVENT_CONSTRAINT 83 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ INTEL_EVENT_CONSTRAINT 100 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ INTEL_EVENT_CONSTRAINT 101 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ INTEL_EVENT_CONSTRAINT 102 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ INTEL_EVENT_CONSTRAINT 103 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ INTEL_EVENT_CONSTRAINT 116 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ INTEL_EVENT_CONSTRAINT 118 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ INTEL_EVENT_CONSTRAINT 201 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ INTEL_EVENT_CONSTRAINT 202 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ INTEL_EVENT_CONSTRAINT 203 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ INTEL_EVENT_CONSTRAINT 204 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ INTEL_EVENT_CONSTRAINT 205 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ INTEL_EVENT_CONSTRAINT 252 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ INTEL_EVENT_CONSTRAINT 257 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ INTEL_EVENT_CONSTRAINT 335 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ INTEL_EVENT_CONSTRAINT 364 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ INTEL_EVENT_CONSTRAINT 365 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ INTEL_EVENT_CONSTRAINT 366 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ INTEL_EVENT_CONSTRAINT 367 arch/x86/events/intel/core.c INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ INTEL_EVENT_CONSTRAINT 721 arch/x86/events/intel/ds.c INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */ INTEL_EVENT_CONSTRAINT 738 arch/x86/events/intel/ds.c INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */ INTEL_EVENT_CONSTRAINT 127 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xc3, 0x1), /* HWP_L2HIT */ INTEL_EVENT_CONSTRAINT 128 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xc4, 0x1), /* HWP_L2MISS */ INTEL_EVENT_CONSTRAINT 129 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xc8, 0x1), /* L2_READ_HIT_E */ INTEL_EVENT_CONSTRAINT 130 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* L2_READ_HIT_M */ INTEL_EVENT_CONSTRAINT 131 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xca, 0x1), /* L2_READ_HIT_S */ INTEL_EVENT_CONSTRAINT 132 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* L2_READ_MISS */ INTEL_EVENT_CONSTRAINT 133 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xcc, 0x1), /* L2_WRITE_HIT */ INTEL_EVENT_CONSTRAINT 134 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xce, 0x1), /* L2_STRONGLY_ORDERED_STREAMING_VSTORES_MISS */ INTEL_EVENT_CONSTRAINT 135 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xcf, 0x1), /* L2_WEAKLY_ORDERED_STREAMING_VSTORE_MISS */ INTEL_EVENT_CONSTRAINT 136 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xd7, 0x1), /* L2_VICTIM_REQ_WITH_DATA */ INTEL_EVENT_CONSTRAINT 137 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xe3, 0x1), /* SNP_HITM_BUNIT */ INTEL_EVENT_CONSTRAINT 138 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xe6, 0x1), /* SNP_HIT_L2 */ INTEL_EVENT_CONSTRAINT 139 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xe7, 0x1), /* SNP_HITM_L2 */ INTEL_EVENT_CONSTRAINT 140 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xf1, 0x1), /* L2_DATA_READ_MISS_CACHE_FILL */ INTEL_EVENT_CONSTRAINT 141 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xf2, 0x1), /* L2_DATA_WRITE_MISS_CACHE_FILL */ INTEL_EVENT_CONSTRAINT 142 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xf6, 0x1), /* L2_DATA_READ_MISS_MEM_FILL */ INTEL_EVENT_CONSTRAINT 143 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xf7, 0x1), /* L2_DATA_WRITE_MISS_MEM_FILL */ INTEL_EVENT_CONSTRAINT 144 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xfc, 0x1), /* L2_DATA_PF2 */ INTEL_EVENT_CONSTRAINT 145 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xfd, 0x1), /* L2_DATA_PF2_DROP */ INTEL_EVENT_CONSTRAINT 146 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xfe, 0x1), /* L2_DATA_PF2_MISS */ INTEL_EVENT_CONSTRAINT 147 arch/x86/events/intel/knc.c INTEL_EVENT_CONSTRAINT(0xff, 0x1), /* L2_DATA_HIT_INFLIGHT_PF2 */ INTEL_EVENT_CONSTRAINT 129 arch/x86/events/intel/p6.c INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FLOPS */ INTEL_EVENT_CONSTRAINT 130 arch/x86/events/intel/p6.c INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ INTEL_EVENT_CONSTRAINT 131 arch/x86/events/intel/p6.c INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ INTEL_EVENT_CONSTRAINT 132 arch/x86/events/intel/p6.c INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ INTEL_EVENT_CONSTRAINT 133 arch/x86/events/intel/p6.c INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ INTEL_EVENT_CONSTRAINT 134 arch/x86/events/intel/p6.c INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */