IMX6SL_CLK_PLL5_VIDEO_DIV  275 drivers/clk/imx/clk-imx6sl.c 	hws[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2,   0, video_div_table, &imx_ccm_lock);
IMX6SL_CLK_PLL5_VIDEO_DIV  443 drivers/clk/imx/clk-imx6sl.c 			hws[IMX6SL_CLK_PLL5_VIDEO_DIV]->clk);