IMX6QDL_CLK_IPU2_DI0_PRE_SEL  664 drivers/clk/imx/clk-imx6q.c 	hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
IMX6QDL_CLK_IPU2_DI0_PRE_SEL  927 drivers/clk/imx/clk-imx6q.c 	clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);