IMGU_REG_BASE 78 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_ISP_CTRL (IMGU_REG_BASE + 0x00) IMGU_REG_BASE 92 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_ISP_START_ADDR (IMGU_REG_BASE + 0x04) IMGU_REG_BASE 93 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_ISP_ICACHE_ADDR (IMGU_REG_BASE + 0x10) IMGU_REG_BASE 94 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_ISP_PC (IMGU_REG_BASE + 0x1c) IMGU_REG_BASE 97 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_SP_CTRL(sp) (IMGU_REG_BASE + (sp) * 0x100 + 0x100) IMGU_REG_BASE 99 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_SP_START_ADDR(sp) (IMGU_REG_BASE + (sp) * 0x100 + 0x104) IMGU_REG_BASE 100 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_SP_ICACHE_ADDR(sp) (IMGU_REG_BASE + (sp) * 0x100 + 0x11c) IMGU_REG_BASE 101 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_SP_CTRL_SINK(sp) (IMGU_REG_BASE + (sp) * 0x100 + 0x130) IMGU_REG_BASE 102 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_SP_PC(sp) (IMGU_REG_BASE + (sp) * 0x100 + 0x134) IMGU_REG_BASE 104 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_TLB_INVALIDATE (IMGU_REG_BASE + 0x300) IMGU_REG_BASE 106 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_L1_PHYS (IMGU_REG_BASE + 0x304) /* 27-bit pfn */ IMGU_REG_BASE 108 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_CIO_GATE_BURST_STATE (IMGU_REG_BASE + 0x404) IMGU_REG_BASE 111 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_GP_BUSY (IMGU_REG_BASE + 0x500) IMGU_REG_BASE 112 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_GP_STARVING (IMGU_REG_BASE + 0x504) IMGU_REG_BASE 113 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_GP_WORKLOAD (IMGU_REG_BASE + 0x508) IMGU_REG_BASE 114 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_GP_IRQ(n) (IMGU_REG_BASE + (n) * 4 + 0x50c) /* n = 0..4 */ IMGU_REG_BASE 115 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_GP_SP1_STRMON_STAT (IMGU_REG_BASE + 0x520) IMGU_REG_BASE 116 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_GP_SP2_STRMON_STAT (IMGU_REG_BASE + 0x524) IMGU_REG_BASE 117 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_GP_ISP_STRMON_STAT (IMGU_REG_BASE + 0x528) IMGU_REG_BASE 118 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_GP_MOD_STRMON_STAT (IMGU_REG_BASE + 0x52c) IMGU_REG_BASE 162 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_GP_HALT (IMGU_REG_BASE + 0x5dc) IMGU_REG_BASE 165 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_IRQCTRL_BASE(n) (IMGU_REG_BASE + (n) * 0x100 + 0x700) IMGU_REG_BASE 205 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_GP_TIMER (IMGU_REG_BASE + 0xa34) IMGU_REG_BASE 207 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_SP_DMEM_BASE(n) (IMGU_REG_BASE + (n) * 0x4000 + 0x4000) IMGU_REG_BASE 208 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_ISP_DMEM_BASE (IMGU_REG_BASE + 0xc000) IMGU_REG_BASE 210 drivers/staging/media/ipu3/ipu3-abi.h #define IMGU_REG_GDC_BASE (IMGU_REG_BASE + 0x18000) IMGU_REG_BASE 42 drivers/staging/media/ipu3/ipu3-mmu.c #define REG_TLB_INVALIDATE (IMGU_REG_BASE + 0x300) IMGU_REG_BASE 44 drivers/staging/media/ipu3/ipu3-mmu.c #define REG_L1_PHYS (IMGU_REG_BASE + 0x304) /* 27-bit pfn */ IMGU_REG_BASE 45 drivers/staging/media/ipu3/ipu3-mmu.c #define REG_GP_HALT (IMGU_REG_BASE + 0x5dc) IMGU_REG_BASE 46 drivers/staging/media/ipu3/ipu3-mmu.c #define REG_GP_HALTED (IMGU_REG_BASE + 0x5e0)