APMU_SDH0 332 drivers/clk/mmp/clk-mmp2.c apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock); APMU_SDH0 336 drivers/clk/mmp/clk-mmp2.c CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0, APMU_SDH0 340 drivers/clk/mmp/clk-mmp2.c clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0, APMU_SDH0 228 drivers/clk/mmp/clk-of-mmp2.c {MMP2_CLK_SDH0, "sdh0_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh_lock}, APMU_SDH0 250 drivers/clk/mmp/clk-of-mmp2.c sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH0; APMU_SDH0 190 drivers/clk/mmp/clk-of-pxa168.c {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock}, APMU_SDH0 206 drivers/clk/mmp/clk-of-pxa168.c {PXA168_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock}, APMU_SDH0 196 drivers/clk/mmp/clk-of-pxa910.c {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock}, APMU_SDH0 212 drivers/clk/mmp/clk-of-pxa910.c {PXA910_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock}, APMU_SDH0 289 drivers/clk/mmp/clk-pxa168.c apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); APMU_SDH0 292 drivers/clk/mmp/clk-pxa168.c clk = mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0, APMU_SDH0 264 drivers/clk/mmp/clk-pxa910.c apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); APMU_SDH0 268 drivers/clk/mmp/clk-pxa910.c apmu_base + APMU_SDH0, 0x1b, &clk_lock);