APMU_DISP1        386 drivers/clk/mmp/clk-mmp2.c 				apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
APMU_DISP1        390 drivers/clk/mmp/clk-mmp2.c 				CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1,
APMU_DISP1        395 drivers/clk/mmp/clk-mmp2.c 				apmu_base + APMU_DISP1, 0x1b, &clk_lock);
APMU_DISP1        214 drivers/clk/mmp/clk-of-mmp2.c 	{MMP2_CLK_DISP1_MUX, "disp1_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP1, 6, 2, 0, &disp1_lock},
APMU_DISP1        220 drivers/clk/mmp/clk-of-mmp2.c 	{0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, 0, &disp1_lock},
APMU_DISP1        235 drivers/clk/mmp/clk-of-mmp2.c 	{MMP2_CLK_DISP1, "disp1_clk", "disp1_div", CLK_SET_RATE_PARENT, APMU_DISP1, 0x09, 0x09, 0x0, 0, &disp1_lock},