APMU_CCIC1        433 drivers/clk/mmp/clk-mmp2.c 				apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
APMU_CCIC1        437 drivers/clk/mmp/clk-mmp2.c 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
APMU_CCIC1        442 drivers/clk/mmp/clk-mmp2.c 				apmu_base + APMU_CCIC1, 0x1b, &clk_lock);
APMU_CCIC1        446 drivers/clk/mmp/clk-mmp2.c 				apmu_base + APMU_CCIC1, 0x24, &clk_lock);
APMU_CCIC1        450 drivers/clk/mmp/clk-mmp2.c 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
APMU_CCIC1        455 drivers/clk/mmp/clk-mmp2.c 				apmu_base + APMU_CCIC1, 0x300, &clk_lock);
APMU_CCIC1        222 drivers/clk/mmp/clk-of-mmp2.c 	{0, "ccic1_sphy_div", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 10, 5, 0, &ccic1_lock},
APMU_CCIC1        240 drivers/clk/mmp/clk-of-mmp2.c 	{MMP2_CLK_CCIC1, "ccic1_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x1b, 0x1b, 0x0, 0, &ccic1_lock},
APMU_CCIC1        241 drivers/clk/mmp/clk-of-mmp2.c 	{MMP2_CLK_CCIC1_PHY, "ccic1_phy_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x24, 0x24, 0x0, 0, &ccic1_lock},
APMU_CCIC1        242 drivers/clk/mmp/clk-of-mmp2.c 	{MMP2_CLK_CCIC1_SPHY, "ccic1_sphy_clk", "ccic1_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x300, 0x300, 0x0, 0, &ccic1_lock},
APMU_CCIC1        263 drivers/clk/mmp/clk-of-mmp2.c 	ccic1_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC1;