APMU_CCIC0        399 drivers/clk/mmp/clk-mmp2.c 				apmu_base + APMU_CCIC0, 0x1800, &clk_lock);
APMU_CCIC0        405 drivers/clk/mmp/clk-mmp2.c 				apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
APMU_CCIC0        409 drivers/clk/mmp/clk-mmp2.c 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
APMU_CCIC0        414 drivers/clk/mmp/clk-mmp2.c 				apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
APMU_CCIC0        418 drivers/clk/mmp/clk-mmp2.c 				apmu_base + APMU_CCIC0, 0x24, &clk_lock);
APMU_CCIC0        422 drivers/clk/mmp/clk-mmp2.c 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
APMU_CCIC0        427 drivers/clk/mmp/clk-mmp2.c 				apmu_base + APMU_CCIC0, 0x300, &clk_lock);
APMU_CCIC0        221 drivers/clk/mmp/clk-of-mmp2.c 	{0, "ccic0_sphy_div", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
APMU_CCIC0        236 drivers/clk/mmp/clk-of-mmp2.c 	{MMP2_CLK_CCIC_ARBITER, "ccic_arbiter", "vctcxo", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1800, 0x1800, 0x0, 0, &ccic0_lock},
APMU_CCIC0        237 drivers/clk/mmp/clk-of-mmp2.c 	{MMP2_CLK_CCIC0, "ccic0_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
APMU_CCIC0        238 drivers/clk/mmp/clk-of-mmp2.c 	{MMP2_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
APMU_CCIC0        239 drivers/clk/mmp/clk-of-mmp2.c 	{MMP2_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
APMU_CCIC0        256 drivers/clk/mmp/clk-of-mmp2.c 	ccic0_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC0;
APMU_CCIC0        193 drivers/clk/mmp/clk-of-pxa168.c 	{0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock},
APMU_CCIC0        194 drivers/clk/mmp/clk-of-pxa168.c 	{0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},
APMU_CCIC0        198 drivers/clk/mmp/clk-of-pxa168.c 	{0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
APMU_CCIC0        209 drivers/clk/mmp/clk-of-pxa168.c 	{PXA168_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
APMU_CCIC0        210 drivers/clk/mmp/clk-of-pxa168.c 	{PXA168_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
APMU_CCIC0        211 drivers/clk/mmp/clk-of-pxa168.c 	{PXA168_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
APMU_CCIC0        199 drivers/clk/mmp/clk-of-pxa910.c 	{0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock},
APMU_CCIC0        200 drivers/clk/mmp/clk-of-pxa910.c 	{0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},
APMU_CCIC0        204 drivers/clk/mmp/clk-of-pxa910.c 	{0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
APMU_CCIC0        215 drivers/clk/mmp/clk-of-pxa910.c 	{PXA910_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
APMU_CCIC0        216 drivers/clk/mmp/clk-of-pxa910.c 	{PXA910_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
APMU_CCIC0        217 drivers/clk/mmp/clk-of-pxa910.c 	{PXA910_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
APMU_CCIC0        331 drivers/clk/mmp/clk-pxa168.c 				apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
APMU_CCIC0        335 drivers/clk/mmp/clk-pxa168.c 				apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
APMU_CCIC0        341 drivers/clk/mmp/clk-pxa168.c 				apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
APMU_CCIC0        345 drivers/clk/mmp/clk-pxa168.c 				apmu_base + APMU_CCIC0, 0x24, &clk_lock);
APMU_CCIC0        349 drivers/clk/mmp/clk-pxa168.c 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
APMU_CCIC0        354 drivers/clk/mmp/clk-pxa168.c 				apmu_base + APMU_CCIC0, 0x300, &clk_lock);
APMU_CCIC0        302 drivers/clk/mmp/clk-pxa910.c 				apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
APMU_CCIC0        306 drivers/clk/mmp/clk-pxa910.c 				apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
APMU_CCIC0        312 drivers/clk/mmp/clk-pxa910.c 				apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
APMU_CCIC0        316 drivers/clk/mmp/clk-pxa910.c 				apmu_base + APMU_CCIC0, 0x24, &clk_lock);
APMU_CCIC0        320 drivers/clk/mmp/clk-pxa910.c 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
APMU_CCIC0        325 drivers/clk/mmp/clk-pxa910.c 				apmu_base + APMU_CCIC0, 0x300, &clk_lock);