ID_AA64PFR1_SSBS_SHIFT  172 arch/arm64/kernel/cpufeature.c 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
ID_AA64PFR1_SSBS_SHIFT 1479 arch/arm64/kernel/cpufeature.c 		.field_pos = ID_AA64PFR1_SSBS_SHIFT,
ID_AA64PFR1_SSBS_SHIFT 1667 arch/arm64/kernel/cpufeature.c 	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),