ID_AA64PFR0_SVE_SHIFT  494 arch/arm64/include/asm/cpufeature.h 	u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_SVE_SHIFT);
ID_AA64PFR0_SVE_SHIFT  158 arch/arm64/kernel/cpufeature.c 				   FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
ID_AA64PFR0_SVE_SHIFT 1400 arch/arm64/kernel/cpufeature.c 		.field_pos = ID_AA64PFR0_SVE_SHIFT,
ID_AA64PFR0_SVE_SHIFT 1659 arch/arm64/kernel/cpufeature.c 	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
ID_AA64PFR0_SVE_SHIFT 1082 arch/arm64/kvm/sys_regs.c 		val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);