ID_AA64ISAR1_SB_SHIFT 136 arch/arm64/kernel/cpufeature.c ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), ID_AA64ISAR1_SB_SHIFT 1504 arch/arm64/kernel/cpufeature.c .field_pos = ID_AA64ISAR1_SB_SHIFT, ID_AA64ISAR1_SB_SHIFT 1656 arch/arm64/kernel/cpufeature.c HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),