IDENT_ADDR 78 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_DCSR (IDENT_ADDR + 0x1A0000000UL) IDENT_ADDR 79 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_PEAR (IDENT_ADDR + 0x1A0000020UL) IDENT_ADDR 80 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_SEAR (IDENT_ADDR + 0x1A0000040UL) IDENT_ADDR 81 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_DR1 (IDENT_ADDR + 0x1A0000060UL) IDENT_ADDR 82 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_DR2 (IDENT_ADDR + 0x1A0000080UL) IDENT_ADDR 83 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_DR3 (IDENT_ADDR + 0x1A00000A0UL) IDENT_ADDR 85 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_TB1R (IDENT_ADDR + 0x1A00000C0UL) IDENT_ADDR 86 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_TB2R (IDENT_ADDR + 0x1A00000E0UL) IDENT_ADDR 88 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_PB1R (IDENT_ADDR + 0x1A0000100UL) IDENT_ADDR 89 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_PB2R (IDENT_ADDR + 0x1A0000120UL) IDENT_ADDR 91 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_PM1R (IDENT_ADDR + 0x1A0000140UL) IDENT_ADDR 92 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_PM2R (IDENT_ADDR + 0x1A0000160UL) IDENT_ADDR 94 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_HAXR0 (IDENT_ADDR + 0x1A0000180UL) IDENT_ADDR 95 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_HAXR1 (IDENT_ADDR + 0x1A00001A0UL) IDENT_ADDR 96 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_HAXR2 (IDENT_ADDR + 0x1A00001C0UL) IDENT_ADDR 98 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_PMLT (IDENT_ADDR + 0x1A00001E0UL) IDENT_ADDR 100 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_TLBTAG0 (IDENT_ADDR + 0x1A0000200UL) IDENT_ADDR 101 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_TLBTAG1 (IDENT_ADDR + 0x1A0000220UL) IDENT_ADDR 102 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_TLBTAG2 (IDENT_ADDR + 0x1A0000240UL) IDENT_ADDR 103 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_TLBTAG3 (IDENT_ADDR + 0x1A0000260UL) IDENT_ADDR 104 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_TLBTAG4 (IDENT_ADDR + 0x1A0000280UL) IDENT_ADDR 105 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_TLBTAG5 (IDENT_ADDR + 0x1A00002A0UL) IDENT_ADDR 106 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_TLBTAG6 (IDENT_ADDR + 0x1A00002C0UL) IDENT_ADDR 107 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_TLBTAG7 (IDENT_ADDR + 0x1A00002E0UL) IDENT_ADDR 109 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_TLBDATA0 (IDENT_ADDR + 0x1A0000300UL) IDENT_ADDR 110 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_TLBDATA1 (IDENT_ADDR + 0x1A0000320UL) IDENT_ADDR 111 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_TLBDATA2 (IDENT_ADDR + 0x1A0000340UL) IDENT_ADDR 112 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_TLBDATA3 (IDENT_ADDR + 0x1A0000360UL) IDENT_ADDR 113 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_TLBDATA4 (IDENT_ADDR + 0x1A0000380UL) IDENT_ADDR 114 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_TLBDATA5 (IDENT_ADDR + 0x1A00003A0UL) IDENT_ADDR 115 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_TLBDATA6 (IDENT_ADDR + 0x1A00003C0UL) IDENT_ADDR 116 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_TLBDATA7 (IDENT_ADDR + 0x1A00003E0UL) IDENT_ADDR 118 arch/alpha/include/asm/core_apecs.h #define APECS_IOC_TBIA (IDENT_ADDR + 0x1A0000400UL) IDENT_ADDR 126 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_GCR (IDENT_ADDR + 0x180000000UL) IDENT_ADDR 127 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_EDSR (IDENT_ADDR + 0x180000040UL) IDENT_ADDR 128 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_TAR (IDENT_ADDR + 0x180000060UL) IDENT_ADDR 129 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_ELAR (IDENT_ADDR + 0x180000080UL) IDENT_ADDR 130 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_EHAR (IDENT_ADDR + 0x1800000a0UL) IDENT_ADDR 131 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_SFT_RST (IDENT_ADDR + 0x1800000c0UL) IDENT_ADDR 132 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_LDxLAR (IDENT_ADDR + 0x1800000e0UL) IDENT_ADDR 133 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_LDxHAR (IDENT_ADDR + 0x180000100UL) IDENT_ADDR 134 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_GTR (IDENT_ADDR + 0x180000200UL) IDENT_ADDR 135 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_RTR (IDENT_ADDR + 0x180000220UL) IDENT_ADDR 136 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_VFPR (IDENT_ADDR + 0x180000240UL) IDENT_ADDR 137 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_PDLDR (IDENT_ADDR + 0x180000260UL) IDENT_ADDR 138 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_PDhDR (IDENT_ADDR + 0x180000280UL) IDENT_ADDR 141 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B0BAR (IDENT_ADDR + 0x180000800UL) IDENT_ADDR 142 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B1BAR (IDENT_ADDR + 0x180000820UL) IDENT_ADDR 143 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B2BAR (IDENT_ADDR + 0x180000840UL) IDENT_ADDR 144 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B3BAR (IDENT_ADDR + 0x180000860UL) IDENT_ADDR 145 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B4BAR (IDENT_ADDR + 0x180000880UL) IDENT_ADDR 146 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B5BAR (IDENT_ADDR + 0x1800008A0UL) IDENT_ADDR 147 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B6BAR (IDENT_ADDR + 0x1800008C0UL) IDENT_ADDR 148 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B7BAR (IDENT_ADDR + 0x1800008E0UL) IDENT_ADDR 149 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B8BAR (IDENT_ADDR + 0x180000900UL) IDENT_ADDR 152 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B0BCR (IDENT_ADDR + 0x180000A00UL) IDENT_ADDR 153 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B1BCR (IDENT_ADDR + 0x180000A20UL) IDENT_ADDR 154 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B2BCR (IDENT_ADDR + 0x180000A40UL) IDENT_ADDR 155 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B3BCR (IDENT_ADDR + 0x180000A60UL) IDENT_ADDR 156 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B4BCR (IDENT_ADDR + 0x180000A80UL) IDENT_ADDR 157 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B5BCR (IDENT_ADDR + 0x180000AA0UL) IDENT_ADDR 158 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B6BCR (IDENT_ADDR + 0x180000AC0UL) IDENT_ADDR 159 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B7BCR (IDENT_ADDR + 0x180000AE0UL) IDENT_ADDR 160 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B8BCR (IDENT_ADDR + 0x180000B00UL) IDENT_ADDR 163 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B0TRA (IDENT_ADDR + 0x180000C00UL) IDENT_ADDR 164 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B1TRA (IDENT_ADDR + 0x180000C20UL) IDENT_ADDR 165 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B2TRA (IDENT_ADDR + 0x180000C40UL) IDENT_ADDR 166 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B3TRA (IDENT_ADDR + 0x180000C60UL) IDENT_ADDR 167 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B4TRA (IDENT_ADDR + 0x180000C80UL) IDENT_ADDR 168 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B5TRA (IDENT_ADDR + 0x180000CA0UL) IDENT_ADDR 169 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B6TRA (IDENT_ADDR + 0x180000CC0UL) IDENT_ADDR 170 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B7TRA (IDENT_ADDR + 0x180000CE0UL) IDENT_ADDR 171 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B8TRA (IDENT_ADDR + 0x180000D00UL) IDENT_ADDR 174 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B0TRB (IDENT_ADDR + 0x180000E00UL) IDENT_ADDR 175 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B1TRB (IDENT_ADDR + 0x180000E20UL) IDENT_ADDR 176 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B2TRB (IDENT_ADDR + 0x180000E40UL) IDENT_ADDR 177 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B3TRB (IDENT_ADDR + 0x180000E60UL) IDENT_ADDR 178 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B4TRB (IDENT_ADDR + 0x180000E80UL) IDENT_ADDR 179 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B5TRB (IDENT_ADDR + 0x180000EA0UL) IDENT_ADDR 180 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B6TRB (IDENT_ADDR + 0x180000EC0UL) IDENT_ADDR 181 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B7TRB (IDENT_ADDR + 0x180000EE0UL) IDENT_ADDR 182 arch/alpha/include/asm/core_apecs.h #define APECS_MEM_B8TRB (IDENT_ADDR + 0x180000F00UL) IDENT_ADDR 188 arch/alpha/include/asm/core_apecs.h #define APECS_IACK_SC (IDENT_ADDR + 0x1b0000000UL) IDENT_ADDR 189 arch/alpha/include/asm/core_apecs.h #define APECS_CONF (IDENT_ADDR + 0x1e0000000UL) IDENT_ADDR 190 arch/alpha/include/asm/core_apecs.h #define APECS_IO (IDENT_ADDR + 0x1c0000000UL) IDENT_ADDR 191 arch/alpha/include/asm/core_apecs.h #define APECS_SPARSE_MEM (IDENT_ADDR + 0x200000000UL) IDENT_ADDR 192 arch/alpha/include/asm/core_apecs.h #define APECS_DENSE_MEM (IDENT_ADDR + 0x300000000UL) IDENT_ADDR 488 arch/alpha/include/asm/core_apecs.h return addr >= IDENT_ADDR + 0x180000000UL; IDENT_ADDR 73 arch/alpha/include/asm/core_cia.h #define CIA_IOC_CIA_REV (IDENT_ADDR + 0x8740000080UL) IDENT_ADDR 75 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_LAT (IDENT_ADDR + 0x87400000C0UL) IDENT_ADDR 76 arch/alpha/include/asm/core_cia.h #define CIA_IOC_CIA_CTRL (IDENT_ADDR + 0x8740000100UL) IDENT_ADDR 101 arch/alpha/include/asm/core_cia.h #define CIA_IOC_CIA_CNFG (IDENT_ADDR + 0x8740000140UL) IDENT_ADDR 106 arch/alpha/include/asm/core_cia.h #define CIA_IOC_FLASH_CTRL (IDENT_ADDR + 0x8740000200UL) IDENT_ADDR 107 arch/alpha/include/asm/core_cia.h #define CIA_IOC_HAE_MEM (IDENT_ADDR + 0x8740000400UL) IDENT_ADDR 108 arch/alpha/include/asm/core_cia.h #define CIA_IOC_HAE_IO (IDENT_ADDR + 0x8740000440UL) IDENT_ADDR 109 arch/alpha/include/asm/core_cia.h #define CIA_IOC_CFG (IDENT_ADDR + 0x8740000480UL) IDENT_ADDR 110 arch/alpha/include/asm/core_cia.h #define CIA_IOC_CACK_EN (IDENT_ADDR + 0x8740000600UL) IDENT_ADDR 120 arch/alpha/include/asm/core_cia.h #define CIA_IOC_CIA_DIAG (IDENT_ADDR + 0x8740002000UL) IDENT_ADDR 121 arch/alpha/include/asm/core_cia.h #define CIA_IOC_DIAG_CHECK (IDENT_ADDR + 0x8740003000UL) IDENT_ADDR 126 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PERF_MONITOR (IDENT_ADDR + 0x8740004000UL) IDENT_ADDR 127 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PERF_CONTROL (IDENT_ADDR + 0x8740004040UL) IDENT_ADDR 132 arch/alpha/include/asm/core_cia.h #define CIA_IOC_CPU_ERR0 (IDENT_ADDR + 0x8740008000UL) IDENT_ADDR 133 arch/alpha/include/asm/core_cia.h #define CIA_IOC_CPU_ERR1 (IDENT_ADDR + 0x8740008040UL) IDENT_ADDR 134 arch/alpha/include/asm/core_cia.h #define CIA_IOC_CIA_ERR (IDENT_ADDR + 0x8740008200UL) IDENT_ADDR 159 arch/alpha/include/asm/core_cia.h #define CIA_IOC_CIA_STAT (IDENT_ADDR + 0x8740008240UL) IDENT_ADDR 160 arch/alpha/include/asm/core_cia.h #define CIA_IOC_ERR_MASK (IDENT_ADDR + 0x8740008280UL) IDENT_ADDR 161 arch/alpha/include/asm/core_cia.h #define CIA_IOC_CIA_SYN (IDENT_ADDR + 0x8740008300UL) IDENT_ADDR 162 arch/alpha/include/asm/core_cia.h #define CIA_IOC_MEM_ERR0 (IDENT_ADDR + 0x8740008400UL) IDENT_ADDR 163 arch/alpha/include/asm/core_cia.h #define CIA_IOC_MEM_ERR1 (IDENT_ADDR + 0x8740008440UL) IDENT_ADDR 164 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_ERR0 (IDENT_ADDR + 0x8740008800UL) IDENT_ADDR 165 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_ERR1 (IDENT_ADDR + 0x8740008840UL) IDENT_ADDR 166 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_ERR3 (IDENT_ADDR + 0x8740008880UL) IDENT_ADDR 171 arch/alpha/include/asm/core_cia.h #define CIA_IOC_MCR (IDENT_ADDR + 0x8750000000UL) IDENT_ADDR 172 arch/alpha/include/asm/core_cia.h #define CIA_IOC_MBA0 (IDENT_ADDR + 0x8750000600UL) IDENT_ADDR 173 arch/alpha/include/asm/core_cia.h #define CIA_IOC_MBA2 (IDENT_ADDR + 0x8750000680UL) IDENT_ADDR 174 arch/alpha/include/asm/core_cia.h #define CIA_IOC_MBA4 (IDENT_ADDR + 0x8750000700UL) IDENT_ADDR 175 arch/alpha/include/asm/core_cia.h #define CIA_IOC_MBA6 (IDENT_ADDR + 0x8750000780UL) IDENT_ADDR 176 arch/alpha/include/asm/core_cia.h #define CIA_IOC_MBA8 (IDENT_ADDR + 0x8750000800UL) IDENT_ADDR 177 arch/alpha/include/asm/core_cia.h #define CIA_IOC_MBAA (IDENT_ADDR + 0x8750000880UL) IDENT_ADDR 178 arch/alpha/include/asm/core_cia.h #define CIA_IOC_MBAC (IDENT_ADDR + 0x8750000900UL) IDENT_ADDR 179 arch/alpha/include/asm/core_cia.h #define CIA_IOC_MBAE (IDENT_ADDR + 0x8750000980UL) IDENT_ADDR 180 arch/alpha/include/asm/core_cia.h #define CIA_IOC_TMG0 (IDENT_ADDR + 0x8750000B00UL) IDENT_ADDR 181 arch/alpha/include/asm/core_cia.h #define CIA_IOC_TMG1 (IDENT_ADDR + 0x8750000B40UL) IDENT_ADDR 182 arch/alpha/include/asm/core_cia.h #define CIA_IOC_TMG2 (IDENT_ADDR + 0x8750000B80UL) IDENT_ADDR 187 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_TBIA (IDENT_ADDR + 0x8760000100UL) IDENT_ADDR 189 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_W0_BASE (IDENT_ADDR + 0x8760000400UL) IDENT_ADDR 190 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_W0_MASK (IDENT_ADDR + 0x8760000440UL) IDENT_ADDR 191 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_T0_BASE (IDENT_ADDR + 0x8760000480UL) IDENT_ADDR 193 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_W1_BASE (IDENT_ADDR + 0x8760000500UL) IDENT_ADDR 194 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_W1_MASK (IDENT_ADDR + 0x8760000540UL) IDENT_ADDR 195 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_T1_BASE (IDENT_ADDR + 0x8760000580UL) IDENT_ADDR 197 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_W2_BASE (IDENT_ADDR + 0x8760000600UL) IDENT_ADDR 198 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_W2_MASK (IDENT_ADDR + 0x8760000640UL) IDENT_ADDR 199 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_T2_BASE (IDENT_ADDR + 0x8760000680UL) IDENT_ADDR 201 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_W3_BASE (IDENT_ADDR + 0x8760000700UL) IDENT_ADDR 202 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_W3_MASK (IDENT_ADDR + 0x8760000740UL) IDENT_ADDR 203 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_T3_BASE (IDENT_ADDR + 0x8760000780UL) IDENT_ADDR 205 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_Wn_BASE(N) (IDENT_ADDR + 0x8760000400UL + (N)*0x100) IDENT_ADDR 206 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_Wn_MASK(N) (IDENT_ADDR + 0x8760000440UL + (N)*0x100) IDENT_ADDR 207 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_Tn_BASE(N) (IDENT_ADDR + 0x8760000480UL + (N)*0x100) IDENT_ADDR 209 arch/alpha/include/asm/core_cia.h #define CIA_IOC_PCI_W_DAC (IDENT_ADDR + 0x87600007C0UL) IDENT_ADDR 217 arch/alpha/include/asm/core_cia.h (IDENT_ADDR + 0x8760000800UL + (n)*0x40) IDENT_ADDR 221 arch/alpha/include/asm/core_cia.h (IDENT_ADDR + 0x8760001000UL + (n)*0x100 + (m)*0x40) IDENT_ADDR 226 arch/alpha/include/asm/core_cia.h #define CIA_IACK_SC (IDENT_ADDR + 0x8720000000UL) IDENT_ADDR 227 arch/alpha/include/asm/core_cia.h #define CIA_CONF (IDENT_ADDR + 0x8700000000UL) IDENT_ADDR 228 arch/alpha/include/asm/core_cia.h #define CIA_IO (IDENT_ADDR + 0x8580000000UL) IDENT_ADDR 229 arch/alpha/include/asm/core_cia.h #define CIA_SPARSE_MEM (IDENT_ADDR + 0x8000000000UL) IDENT_ADDR 230 arch/alpha/include/asm/core_cia.h #define CIA_SPARSE_MEM_R2 (IDENT_ADDR + 0x8400000000UL) IDENT_ADDR 231 arch/alpha/include/asm/core_cia.h #define CIA_SPARSE_MEM_R3 (IDENT_ADDR + 0x8500000000UL) IDENT_ADDR 232 arch/alpha/include/asm/core_cia.h #define CIA_DENSE_MEM (IDENT_ADDR + 0x8600000000UL) IDENT_ADDR 233 arch/alpha/include/asm/core_cia.h #define CIA_BW_MEM (IDENT_ADDR + 0x8800000000UL) IDENT_ADDR 234 arch/alpha/include/asm/core_cia.h #define CIA_BW_IO (IDENT_ADDR + 0x8900000000UL) IDENT_ADDR 235 arch/alpha/include/asm/core_cia.h #define CIA_BW_CFG_0 (IDENT_ADDR + 0x8a00000000UL) IDENT_ADDR 236 arch/alpha/include/asm/core_cia.h #define CIA_BW_CFG_1 (IDENT_ADDR + 0x8b00000000UL) IDENT_ADDR 241 arch/alpha/include/asm/core_cia.h #define GRU_INT_REQ (IDENT_ADDR + 0x8780000000UL) IDENT_ADDR 242 arch/alpha/include/asm/core_cia.h #define GRU_INT_MASK (IDENT_ADDR + 0x8780000040UL) IDENT_ADDR 243 arch/alpha/include/asm/core_cia.h #define GRU_INT_EDGE (IDENT_ADDR + 0x8780000080UL) IDENT_ADDR 244 arch/alpha/include/asm/core_cia.h #define GRU_INT_HILO (IDENT_ADDR + 0x87800000C0UL) IDENT_ADDR 245 arch/alpha/include/asm/core_cia.h #define GRU_INT_CLEAR (IDENT_ADDR + 0x8780000100UL) IDENT_ADDR 247 arch/alpha/include/asm/core_cia.h #define GRU_CACHE_CNFG (IDENT_ADDR + 0x8780000200UL) IDENT_ADDR 248 arch/alpha/include/asm/core_cia.h #define GRU_SCR (IDENT_ADDR + 0x8780000300UL) IDENT_ADDR 249 arch/alpha/include/asm/core_cia.h #define GRU_LED (IDENT_ADDR + 0x8780000800UL) IDENT_ADDR 250 arch/alpha/include/asm/core_cia.h #define GRU_RESET (IDENT_ADDR + 0x8780000900UL) IDENT_ADDR 259 arch/alpha/include/asm/core_cia.h #define PYXIS_INT_REQ (IDENT_ADDR + 0x87A0000000UL) IDENT_ADDR 260 arch/alpha/include/asm/core_cia.h #define PYXIS_INT_MASK (IDENT_ADDR + 0x87A0000040UL) IDENT_ADDR 261 arch/alpha/include/asm/core_cia.h #define PYXIS_INT_HILO (IDENT_ADDR + 0x87A00000C0UL) IDENT_ADDR 262 arch/alpha/include/asm/core_cia.h #define PYXIS_INT_ROUTE (IDENT_ADDR + 0x87A0000140UL) IDENT_ADDR 263 arch/alpha/include/asm/core_cia.h #define PYXIS_GPO (IDENT_ADDR + 0x87A0000180UL) IDENT_ADDR 264 arch/alpha/include/asm/core_cia.h #define PYXIS_INT_CNFG (IDENT_ADDR + 0x87A00001C0UL) IDENT_ADDR 265 arch/alpha/include/asm/core_cia.h #define PYXIS_RT_COUNT (IDENT_ADDR + 0x87A0000200UL) IDENT_ADDR 266 arch/alpha/include/asm/core_cia.h #define PYXIS_INT_TIME (IDENT_ADDR + 0x87A0000240UL) IDENT_ADDR 267 arch/alpha/include/asm/core_cia.h #define PYXIS_IIC_CTRL (IDENT_ADDR + 0x87A00002C0UL) IDENT_ADDR 268 arch/alpha/include/asm/core_cia.h #define PYXIS_RESET (IDENT_ADDR + 0x8780000900UL) IDENT_ADDR 436 arch/alpha/include/asm/core_cia.h return addr >= IDENT_ADDR + 0x8000000000UL; IDENT_ADDR 457 arch/alpha/include/asm/core_cia.h return addr >= IDENT_ADDR + 0x8000000000UL; IDENT_ADDR 124 arch/alpha/include/asm/core_irongate.h #define IRONGATE_MEM (IDENT_ADDR | IRONGATE_BIAS | 0x000000000UL) IDENT_ADDR 125 arch/alpha/include/asm/core_irongate.h #define IRONGATE_IACK_SC (IDENT_ADDR | IRONGATE_BIAS | 0x1F8000000UL) IDENT_ADDR 126 arch/alpha/include/asm/core_irongate.h #define IRONGATE_IO (IDENT_ADDR | IRONGATE_BIAS | 0x1FC000000UL) IDENT_ADDR 127 arch/alpha/include/asm/core_irongate.h #define IRONGATE_CONF (IDENT_ADDR | IRONGATE_BIAS | 0x1FE000000UL) IDENT_ADDR 62 arch/alpha/include/asm/core_lca.h #define LCA_MEM_BCR0 (IDENT_ADDR + 0x120000000UL) IDENT_ADDR 63 arch/alpha/include/asm/core_lca.h #define LCA_MEM_BCR1 (IDENT_ADDR + 0x120000008UL) IDENT_ADDR 64 arch/alpha/include/asm/core_lca.h #define LCA_MEM_BCR2 (IDENT_ADDR + 0x120000010UL) IDENT_ADDR 65 arch/alpha/include/asm/core_lca.h #define LCA_MEM_BCR3 (IDENT_ADDR + 0x120000018UL) IDENT_ADDR 66 arch/alpha/include/asm/core_lca.h #define LCA_MEM_BMR0 (IDENT_ADDR + 0x120000020UL) IDENT_ADDR 67 arch/alpha/include/asm/core_lca.h #define LCA_MEM_BMR1 (IDENT_ADDR + 0x120000028UL) IDENT_ADDR 68 arch/alpha/include/asm/core_lca.h #define LCA_MEM_BMR2 (IDENT_ADDR + 0x120000030UL) IDENT_ADDR 69 arch/alpha/include/asm/core_lca.h #define LCA_MEM_BMR3 (IDENT_ADDR + 0x120000038UL) IDENT_ADDR 70 arch/alpha/include/asm/core_lca.h #define LCA_MEM_BTR0 (IDENT_ADDR + 0x120000040UL) IDENT_ADDR 71 arch/alpha/include/asm/core_lca.h #define LCA_MEM_BTR1 (IDENT_ADDR + 0x120000048UL) IDENT_ADDR 72 arch/alpha/include/asm/core_lca.h #define LCA_MEM_BTR2 (IDENT_ADDR + 0x120000050UL) IDENT_ADDR 73 arch/alpha/include/asm/core_lca.h #define LCA_MEM_BTR3 (IDENT_ADDR + 0x120000058UL) IDENT_ADDR 74 arch/alpha/include/asm/core_lca.h #define LCA_MEM_GTR (IDENT_ADDR + 0x120000060UL) IDENT_ADDR 75 arch/alpha/include/asm/core_lca.h #define LCA_MEM_ESR (IDENT_ADDR + 0x120000068UL) IDENT_ADDR 76 arch/alpha/include/asm/core_lca.h #define LCA_MEM_EAR (IDENT_ADDR + 0x120000070UL) IDENT_ADDR 77 arch/alpha/include/asm/core_lca.h #define LCA_MEM_CAR (IDENT_ADDR + 0x120000078UL) IDENT_ADDR 78 arch/alpha/include/asm/core_lca.h #define LCA_MEM_VGR (IDENT_ADDR + 0x120000080UL) IDENT_ADDR 79 arch/alpha/include/asm/core_lca.h #define LCA_MEM_PLM (IDENT_ADDR + 0x120000088UL) IDENT_ADDR 80 arch/alpha/include/asm/core_lca.h #define LCA_MEM_FOR (IDENT_ADDR + 0x120000090UL) IDENT_ADDR 85 arch/alpha/include/asm/core_lca.h #define LCA_IOC_HAE (IDENT_ADDR + 0x180000000UL) IDENT_ADDR 86 arch/alpha/include/asm/core_lca.h #define LCA_IOC_CONF (IDENT_ADDR + 0x180000020UL) IDENT_ADDR 87 arch/alpha/include/asm/core_lca.h #define LCA_IOC_STAT0 (IDENT_ADDR + 0x180000040UL) IDENT_ADDR 88 arch/alpha/include/asm/core_lca.h #define LCA_IOC_STAT1 (IDENT_ADDR + 0x180000060UL) IDENT_ADDR 89 arch/alpha/include/asm/core_lca.h #define LCA_IOC_TBIA (IDENT_ADDR + 0x180000080UL) IDENT_ADDR 90 arch/alpha/include/asm/core_lca.h #define LCA_IOC_TB_ENA (IDENT_ADDR + 0x1800000a0UL) IDENT_ADDR 91 arch/alpha/include/asm/core_lca.h #define LCA_IOC_SFT_RST (IDENT_ADDR + 0x1800000c0UL) IDENT_ADDR 92 arch/alpha/include/asm/core_lca.h #define LCA_IOC_PAR_DIS (IDENT_ADDR + 0x1800000e0UL) IDENT_ADDR 93 arch/alpha/include/asm/core_lca.h #define LCA_IOC_W_BASE0 (IDENT_ADDR + 0x180000100UL) IDENT_ADDR 94 arch/alpha/include/asm/core_lca.h #define LCA_IOC_W_BASE1 (IDENT_ADDR + 0x180000120UL) IDENT_ADDR 95 arch/alpha/include/asm/core_lca.h #define LCA_IOC_W_MASK0 (IDENT_ADDR + 0x180000140UL) IDENT_ADDR 96 arch/alpha/include/asm/core_lca.h #define LCA_IOC_W_MASK1 (IDENT_ADDR + 0x180000160UL) IDENT_ADDR 97 arch/alpha/include/asm/core_lca.h #define LCA_IOC_T_BASE0 (IDENT_ADDR + 0x180000180UL) IDENT_ADDR 98 arch/alpha/include/asm/core_lca.h #define LCA_IOC_T_BASE1 (IDENT_ADDR + 0x1800001a0UL) IDENT_ADDR 99 arch/alpha/include/asm/core_lca.h #define LCA_IOC_TB_TAG0 (IDENT_ADDR + 0x188000000UL) IDENT_ADDR 100 arch/alpha/include/asm/core_lca.h #define LCA_IOC_TB_TAG1 (IDENT_ADDR + 0x188000020UL) IDENT_ADDR 101 arch/alpha/include/asm/core_lca.h #define LCA_IOC_TB_TAG2 (IDENT_ADDR + 0x188000040UL) IDENT_ADDR 102 arch/alpha/include/asm/core_lca.h #define LCA_IOC_TB_TAG3 (IDENT_ADDR + 0x188000060UL) IDENT_ADDR 103 arch/alpha/include/asm/core_lca.h #define LCA_IOC_TB_TAG4 (IDENT_ADDR + 0x188000070UL) IDENT_ADDR 104 arch/alpha/include/asm/core_lca.h #define LCA_IOC_TB_TAG5 (IDENT_ADDR + 0x1880000a0UL) IDENT_ADDR 105 arch/alpha/include/asm/core_lca.h #define LCA_IOC_TB_TAG6 (IDENT_ADDR + 0x1880000c0UL) IDENT_ADDR 106 arch/alpha/include/asm/core_lca.h #define LCA_IOC_TB_TAG7 (IDENT_ADDR + 0x1880000e0UL) IDENT_ADDR 111 arch/alpha/include/asm/core_lca.h #define LCA_IACK_SC (IDENT_ADDR + 0x1a0000000UL) IDENT_ADDR 112 arch/alpha/include/asm/core_lca.h #define LCA_CONF (IDENT_ADDR + 0x1e0000000UL) IDENT_ADDR 113 arch/alpha/include/asm/core_lca.h #define LCA_IO (IDENT_ADDR + 0x1c0000000UL) IDENT_ADDR 114 arch/alpha/include/asm/core_lca.h #define LCA_SPARSE_MEM (IDENT_ADDR + 0x200000000UL) IDENT_ADDR 115 arch/alpha/include/asm/core_lca.h #define LCA_DENSE_MEM (IDENT_ADDR + 0x300000000UL) IDENT_ADDR 133 arch/alpha/include/asm/core_lca.h #define LCA_PMR_ADDR (IDENT_ADDR + 0x120000098UL) IDENT_ADDR 334 arch/alpha/include/asm/core_lca.h return addr >= IDENT_ADDR + 0x120000000UL; IDENT_ADDR 54 arch/alpha/include/asm/core_marvel.h #define EV7_KERN_ADDR(addr) ((void *)(IDENT_ADDR | EV7_MASK40(addr))) IDENT_ADDR 89 arch/alpha/include/asm/core_mcpcia.h #define MCPCIA_SPARSE(m) (IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m)) IDENT_ADDR 90 arch/alpha/include/asm/core_mcpcia.h #define MCPCIA_DENSE(m) (IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m)) IDENT_ADDR 91 arch/alpha/include/asm/core_mcpcia.h #define MCPCIA_IO(m) (IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m)) IDENT_ADDR 92 arch/alpha/include/asm/core_mcpcia.h #define MCPCIA_CONF(m) (IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m)) IDENT_ADDR 93 arch/alpha/include/asm/core_mcpcia.h #define MCPCIA_CSR(m) (IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m)) IDENT_ADDR 94 arch/alpha/include/asm/core_mcpcia.h #define MCPCIA_IO_IACK(m) (IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m)) IDENT_ADDR 95 arch/alpha/include/asm/core_mcpcia.h #define MCPCIA_DENSE_IO(m) (IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m)) IDENT_ADDR 96 arch/alpha/include/asm/core_mcpcia.h #define MCPCIA_DENSE_CONF(m) (IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m)) IDENT_ADDR 22 arch/alpha/include/asm/core_polaris.h #define POLARIS_SPARSE_MEM_BASE (IDENT_ADDR + 0xf800000000UL) IDENT_ADDR 23 arch/alpha/include/asm/core_polaris.h #define POLARIS_DENSE_MEM_BASE (IDENT_ADDR + 0xf900000000UL) IDENT_ADDR 24 arch/alpha/include/asm/core_polaris.h #define POLARIS_SPARSE_IO_BASE (IDENT_ADDR + 0xf980000000UL) IDENT_ADDR 25 arch/alpha/include/asm/core_polaris.h #define POLARIS_SPARSE_CONFIG_BASE (IDENT_ADDR + 0xf9c0000000UL) IDENT_ADDR 26 arch/alpha/include/asm/core_polaris.h #define POLARIS_IACK_BASE (IDENT_ADDR + 0xf9f8000000UL) IDENT_ADDR 27 arch/alpha/include/asm/core_polaris.h #define POLARIS_DENSE_IO_BASE (IDENT_ADDR + 0xf9fc000000UL) IDENT_ADDR 28 arch/alpha/include/asm/core_polaris.h #define POLARIS_DENSE_CONFIG_BASE (IDENT_ADDR + 0xf9fe000000UL) IDENT_ADDR 42 arch/alpha/include/asm/core_t2.h #define T2_CONF (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL) IDENT_ADDR 43 arch/alpha/include/asm/core_t2.h #define T2_IO (IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL) IDENT_ADDR 44 arch/alpha/include/asm/core_t2.h #define T2_SPARSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x200000000UL) IDENT_ADDR 45 arch/alpha/include/asm/core_t2.h #define T2_DENSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL) IDENT_ADDR 47 arch/alpha/include/asm/core_t2.h #define T2_IOCSR (IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL) IDENT_ADDR 48 arch/alpha/include/asm/core_t2.h #define T2_CERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL) IDENT_ADDR 49 arch/alpha/include/asm/core_t2.h #define T2_CERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL) IDENT_ADDR 50 arch/alpha/include/asm/core_t2.h #define T2_CERR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL) IDENT_ADDR 51 arch/alpha/include/asm/core_t2.h #define T2_PERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL) IDENT_ADDR 52 arch/alpha/include/asm/core_t2.h #define T2_PERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000a0UL) IDENT_ADDR 53 arch/alpha/include/asm/core_t2.h #define T2_PSCR (IDENT_ADDR + GAMMA_BIAS + 0x38e0000c0UL) IDENT_ADDR 54 arch/alpha/include/asm/core_t2.h #define T2_HAE_1 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000e0UL) IDENT_ADDR 55 arch/alpha/include/asm/core_t2.h #define T2_HAE_2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000100UL) IDENT_ADDR 56 arch/alpha/include/asm/core_t2.h #define T2_HBASE (IDENT_ADDR + GAMMA_BIAS + 0x38e000120UL) IDENT_ADDR 57 arch/alpha/include/asm/core_t2.h #define T2_WBASE1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000140UL) IDENT_ADDR 58 arch/alpha/include/asm/core_t2.h #define T2_WMASK1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000160UL) IDENT_ADDR 59 arch/alpha/include/asm/core_t2.h #define T2_TBASE1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000180UL) IDENT_ADDR 60 arch/alpha/include/asm/core_t2.h #define T2_WBASE2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001a0UL) IDENT_ADDR 61 arch/alpha/include/asm/core_t2.h #define T2_WMASK2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001c0UL) IDENT_ADDR 62 arch/alpha/include/asm/core_t2.h #define T2_TBASE2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001e0UL) IDENT_ADDR 63 arch/alpha/include/asm/core_t2.h #define T2_TLBBR (IDENT_ADDR + GAMMA_BIAS + 0x38e000200UL) IDENT_ADDR 64 arch/alpha/include/asm/core_t2.h #define T2_IVR (IDENT_ADDR + GAMMA_BIAS + 0x38e000220UL) IDENT_ADDR 65 arch/alpha/include/asm/core_t2.h #define T2_HAE_3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000240UL) IDENT_ADDR 66 arch/alpha/include/asm/core_t2.h #define T2_HAE_4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000260UL) IDENT_ADDR 69 arch/alpha/include/asm/core_t2.h #define T2_WBASE3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000280UL) IDENT_ADDR 70 arch/alpha/include/asm/core_t2.h #define T2_WMASK3 (IDENT_ADDR + GAMMA_BIAS + 0x38e0002a0UL) IDENT_ADDR 71 arch/alpha/include/asm/core_t2.h #define T2_TBASE3 (IDENT_ADDR + GAMMA_BIAS + 0x38e0002c0UL) IDENT_ADDR 73 arch/alpha/include/asm/core_t2.h #define T2_TDR0 (IDENT_ADDR + GAMMA_BIAS + 0x38e000300UL) IDENT_ADDR 74 arch/alpha/include/asm/core_t2.h #define T2_TDR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000320UL) IDENT_ADDR 75 arch/alpha/include/asm/core_t2.h #define T2_TDR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000340UL) IDENT_ADDR 76 arch/alpha/include/asm/core_t2.h #define T2_TDR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000360UL) IDENT_ADDR 77 arch/alpha/include/asm/core_t2.h #define T2_TDR4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000380UL) IDENT_ADDR 78 arch/alpha/include/asm/core_t2.h #define T2_TDR5 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003a0UL) IDENT_ADDR 79 arch/alpha/include/asm/core_t2.h #define T2_TDR6 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003c0UL) IDENT_ADDR 80 arch/alpha/include/asm/core_t2.h #define T2_TDR7 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003e0UL) IDENT_ADDR 82 arch/alpha/include/asm/core_t2.h #define T2_WBASE4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000400UL) IDENT_ADDR 83 arch/alpha/include/asm/core_t2.h #define T2_WMASK4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000420UL) IDENT_ADDR 84 arch/alpha/include/asm/core_t2.h #define T2_TBASE4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000440UL) IDENT_ADDR 86 arch/alpha/include/asm/core_t2.h #define T2_AIR (IDENT_ADDR + GAMMA_BIAS + 0x38e000460UL) IDENT_ADDR 87 arch/alpha/include/asm/core_t2.h #define T2_VAR (IDENT_ADDR + GAMMA_BIAS + 0x38e000480UL) IDENT_ADDR 88 arch/alpha/include/asm/core_t2.h #define T2_DIR (IDENT_ADDR + GAMMA_BIAS + 0x38e0004a0UL) IDENT_ADDR 89 arch/alpha/include/asm/core_t2.h #define T2_ICE (IDENT_ADDR + GAMMA_BIAS + 0x38e0004c0UL) IDENT_ADDR 128 arch/alpha/include/asm/core_t2.h #define T2_CPU0_BASE (IDENT_ADDR + GAMMA_BIAS + 0x380000000L) IDENT_ADDR 129 arch/alpha/include/asm/core_t2.h #define T2_CPU1_BASE (IDENT_ADDR + GAMMA_BIAS + 0x381000000L) IDENT_ADDR 130 arch/alpha/include/asm/core_t2.h #define T2_CPU2_BASE (IDENT_ADDR + GAMMA_BIAS + 0x382000000L) IDENT_ADDR 131 arch/alpha/include/asm/core_t2.h #define T2_CPU3_BASE (IDENT_ADDR + GAMMA_BIAS + 0x383000000L) IDENT_ADDR 135 arch/alpha/include/asm/core_t2.h #define T2_MEM0_BASE (IDENT_ADDR + GAMMA_BIAS + 0x388000000L) IDENT_ADDR 136 arch/alpha/include/asm/core_t2.h #define T2_MEM1_BASE (IDENT_ADDR + GAMMA_BIAS + 0x389000000L) IDENT_ADDR 137 arch/alpha/include/asm/core_t2.h #define T2_MEM2_BASE (IDENT_ADDR + GAMMA_BIAS + 0x38a000000L) IDENT_ADDR 138 arch/alpha/include/asm/core_t2.h #define T2_MEM3_BASE (IDENT_ADDR + GAMMA_BIAS + 0x38b000000L) IDENT_ADDR 127 arch/alpha/include/asm/core_titan.h #define TITAN_cchip ((titan_cchip *)(IDENT_ADDR+TI_BIAS+0x1A0000000UL)) IDENT_ADDR 128 arch/alpha/include/asm/core_titan.h #define TITAN_dchip ((titan_dchip *)(IDENT_ADDR+TI_BIAS+0x1B0000800UL)) IDENT_ADDR 129 arch/alpha/include/asm/core_titan.h #define TITAN_pachip0 ((titan_pachip *)(IDENT_ADDR+TI_BIAS+0x180000000UL)) IDENT_ADDR 130 arch/alpha/include/asm/core_titan.h #define TITAN_pachip1 ((titan_pachip *)(IDENT_ADDR+TI_BIAS+0x380000000UL)) IDENT_ADDR 299 arch/alpha/include/asm/core_titan.h #define TITAN_BASE (IDENT_ADDR + TI_BIAS) IDENT_ADDR 89 arch/alpha/include/asm/core_tsunami.h #define TSUNAMI_cchip ((tsunami_cchip *)(IDENT_ADDR+TS_BIAS+0x1A0000000UL)) IDENT_ADDR 90 arch/alpha/include/asm/core_tsunami.h #define TSUNAMI_dchip ((tsunami_dchip *)(IDENT_ADDR+TS_BIAS+0x1B0000800UL)) IDENT_ADDR 91 arch/alpha/include/asm/core_tsunami.h #define TSUNAMI_pchip0 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x180000000UL)) IDENT_ADDR 92 arch/alpha/include/asm/core_tsunami.h #define TSUNAMI_pchip1 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x380000000UL)) IDENT_ADDR 257 arch/alpha/include/asm/core_tsunami.h #define TSUNAMI_BASE (IDENT_ADDR + TS_BIAS) IDENT_ADDR 223 arch/alpha/include/asm/core_wildfire.h #define WILDFIRE_BASE (IDENT_ADDR | (1UL << 40)) IDENT_ADDR 127 arch/alpha/include/asm/dma.h ~0UL : IDENT_ADDR + 0x01000000) IDENT_ADDR 66 arch/alpha/include/asm/io.h return (unsigned long)address - IDENT_ADDR; IDENT_ADDR 71 arch/alpha/include/asm/io.h return (void *) (address + IDENT_ADDR); IDENT_ADDR 90 arch/alpha/include/asm/io.h return (void *)(IDENT_ADDR + (address & ((1ul << 41) - 1))); IDENT_ADDR 34 arch/alpha/include/asm/jensen.h #define EISA_INTA (IDENT_ADDR + 0x100000000UL) IDENT_ADDR 39 arch/alpha/include/asm/jensen.h #define EISA_FEPROM0 (IDENT_ADDR + 0x180000000UL) IDENT_ADDR 40 arch/alpha/include/asm/jensen.h #define EISA_FEPROM1 (IDENT_ADDR + 0x1A0000000UL) IDENT_ADDR 45 arch/alpha/include/asm/jensen.h #define EISA_VL82C106 (IDENT_ADDR + 0x1C0000000UL) IDENT_ADDR 50 arch/alpha/include/asm/jensen.h #define EISA_HAE (IDENT_ADDR + 0x1D0000000UL) IDENT_ADDR 55 arch/alpha/include/asm/jensen.h #define EISA_SYSCTL (IDENT_ADDR + 0x1E0000000UL) IDENT_ADDR 60 arch/alpha/include/asm/jensen.h #define EISA_SPARE (IDENT_ADDR + 0x1F0000000UL) IDENT_ADDR 65 arch/alpha/include/asm/jensen.h #define EISA_MEM (IDENT_ADDR + 0x200000000UL) IDENT_ADDR 70 arch/alpha/include/asm/jensen.h #define EISA_IO (IDENT_ADDR + 0x300000000UL) IDENT_ADDR 241 arch/alpha/include/asm/mmu_context.h = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT; IDENT_ADDR 255 arch/alpha/include/asm/mmu_context.h = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT; IDENT_ADDR 338 arch/alpha/kernel/core_apecs.c hose->sparse_mem_base = APECS_SPARSE_MEM - IDENT_ADDR; IDENT_ADDR 339 arch/alpha/kernel/core_apecs.c hose->dense_mem_base = APECS_DENSE_MEM - IDENT_ADDR; IDENT_ADDR 340 arch/alpha/kernel/core_apecs.c hose->sparse_io_base = APECS_IO - IDENT_ADDR; IDENT_ADDR 704 arch/alpha/kernel/core_cia.c hose->sparse_mem_base = CIA_SPARSE_MEM - IDENT_ADDR; IDENT_ADDR 705 arch/alpha/kernel/core_cia.c hose->dense_mem_base = CIA_DENSE_MEM - IDENT_ADDR; IDENT_ADDR 706 arch/alpha/kernel/core_cia.c hose->sparse_io_base = CIA_IO - IDENT_ADDR; IDENT_ADDR 710 arch/alpha/kernel/core_cia.c hose->dense_mem_base = CIA_BW_MEM - IDENT_ADDR; IDENT_ADDR 712 arch/alpha/kernel/core_cia.c hose->dense_io_base = CIA_BW_IO - IDENT_ADDR; IDENT_ADDR 263 arch/alpha/kernel/core_lca.c hose->sparse_mem_base = LCA_SPARSE_MEM - IDENT_ADDR; IDENT_ADDR 264 arch/alpha/kernel/core_lca.c hose->dense_mem_base = LCA_DENSE_MEM - IDENT_ADDR; IDENT_ADDR 265 arch/alpha/kernel/core_lca.c hose->sparse_io_base = LCA_IO - IDENT_ADDR; IDENT_ADDR 722 arch/alpha/kernel/core_marvel.c addr = IDENT_ADDR | (baddr - __direct_map_base); IDENT_ADDR 304 arch/alpha/kernel/core_mcpcia.c hose->sparse_mem_base = MCPCIA_SPARSE(mid) - IDENT_ADDR; IDENT_ADDR 305 arch/alpha/kernel/core_mcpcia.c hose->dense_mem_base = MCPCIA_DENSE(mid) - IDENT_ADDR; IDENT_ADDR 306 arch/alpha/kernel/core_mcpcia.c hose->sparse_io_base = MCPCIA_IO(mid) - IDENT_ADDR; IDENT_ADDR 169 arch/alpha/kernel/core_polaris.c hose->dense_mem_base = POLARIS_DENSE_MEM_BASE - IDENT_ADDR; IDENT_ADDR 171 arch/alpha/kernel/core_polaris.c hose->dense_io_base = POLARIS_DENSE_IO_BASE - IDENT_ADDR; IDENT_ADDR 446 arch/alpha/kernel/core_t2.c hose->sparse_mem_base = T2_SPARSE_MEM - IDENT_ADDR; IDENT_ADDR 447 arch/alpha/kernel/core_t2.c hose->dense_mem_base = T2_DENSE_MEM - IDENT_ADDR; IDENT_ADDR 448 arch/alpha/kernel/core_t2.c hose->sparse_io_base = T2_IO - IDENT_ADDR; IDENT_ADDR 245 arch/alpha/kernel/err_common.c (IDENT_ADDR | pcpu->console_data_log_pa); IDENT_ADDR 846 arch/alpha/kernel/pci_iommu.c if (!__direct_map_base && MAX_DMA_ADDRESS - IDENT_ADDR - 1 <= mask) IDENT_ADDR 201 arch/alpha/kernel/sys_jensen.c hose->sparse_mem_base = EISA_MEM - IDENT_ADDR; IDENT_ADDR 203 arch/alpha/kernel/sys_jensen.c hose->sparse_io_base = EISA_IO - IDENT_ADDR; IDENT_ADDR 51 arch/alpha/mm/fault.c pcb->ptbr = ((unsigned long) next_mm->pgd - IDENT_ADDR) >> PAGE_SHIFT;