ICACHE 11 arch/csky/include/uapi/asm/cachectl.h #define BCACHE (ICACHE|DCACHE) ICACHE 15 arch/csky/mm/syscache.c case ICACHE: ICACHE 17 arch/mips/include/uapi/asm/cachectl.h #define BCACHE (ICACHE|DCACHE) /* flush both caches */ ICACHE 38 arch/nds32/include/asm/nds32.h if (cache == ICACHE) ICACHE 49 arch/nds32/include/asm/nds32.h if (cache == ICACHE) ICACHE 60 arch/nds32/include/asm/nds32.h if (cache == ICACHE) ICACHE 11 arch/nds32/kernel/cacheinfo.c char cache_type = (type & CACHE_TYPE_INST ? ICACHE : DCACHE); ICACHE 104 arch/nds32/kernel/setup.c L1_cache_info[ICACHE].ways = CACHE_WAY(ICACHE); ICACHE 105 arch/nds32/kernel/setup.c L1_cache_info[ICACHE].line_size = CACHE_LINE_SIZE(ICACHE); ICACHE 106 arch/nds32/kernel/setup.c L1_cache_info[ICACHE].sets = CACHE_SET(ICACHE); ICACHE 107 arch/nds32/kernel/setup.c L1_cache_info[ICACHE].size = ICACHE 108 arch/nds32/kernel/setup.c L1_cache_info[ICACHE].ways * L1_cache_info[ICACHE].line_size * ICACHE 109 arch/nds32/kernel/setup.c L1_cache_info[ICACHE].sets / 1024; ICACHE 110 arch/nds32/kernel/setup.c pr_info("L1I:%dKB/%dS/%dW/%dB\n", L1_cache_info[ICACHE].size, ICACHE 111 arch/nds32/kernel/setup.c L1_cache_info[ICACHE].sets, L1_cache_info[ICACHE].ways, ICACHE 112 arch/nds32/kernel/setup.c L1_cache_info[ICACHE].line_size); ICACHE 131 arch/nds32/kernel/setup.c L1_cache_info[ICACHE].size * 1024 / PAGE_SIZE / ICACHE 132 arch/nds32/kernel/setup.c L1_cache_info[ICACHE].ways; ICACHE 133 arch/nds32/kernel/setup.c L1_cache_info[ICACHE].aliasing_num = aliasing_num; ICACHE 134 arch/nds32/kernel/setup.c L1_cache_info[ICACHE].aliasing_mask = ICACHE 337 arch/nds32/kernel/setup.c CACHE_SET(ICACHE) * CACHE_WAY(ICACHE) * ICACHE 338 arch/nds32/kernel/setup.c CACHE_LINE_SIZE(ICACHE) / 1024, CACHE_SET(ICACHE), ICACHE 339 arch/nds32/kernel/setup.c CACHE_WAY(ICACHE), CACHE_LINE_SIZE(ICACHE)); ICACHE 38 arch/nds32/kernel/sys_nds32.c case ICACHE: ICACHE 102 arch/nds32/mm/proc.c line_size = L1_cache_info[ICACHE].line_size; ICACHE 104 arch/nds32/mm/proc.c line_size * L1_cache_info[ICACHE].ways * L1_cache_info[ICACHE].sets; ICACHE 176 arch/nds32/mm/proc.c line_size = L1_cache_info[ICACHE].line_size; ICACHE 279 arch/nds32/mm/proc.c line_size = L1_cache_info[ICACHE].line_size; ICACHE 341 arch/nds32/mm/proc.c line_size = L1_cache_info[ICACHE].line_size; ICACHE 18 arch/sh/include/uapi/asm/cachectl.h #define BCACHE (ICACHE|DCACHE) /* flush both caches */