APBC_UART2 270 drivers/clk/mmp/clk-mmp2.c apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); APBC_UART2 275 drivers/clk/mmp/clk-mmp2.c apbc_base + APBC_UART2, 10, 0, &clk_lock); APBC_UART2 144 drivers/clk/mmp/clk-of-mmp2.c {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock}, APBC_UART2 170 drivers/clk/mmp/clk-of-mmp2.c {MMP2_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x7, 0x3, 0x0, 0, &uart2_lock}, APBC_UART2 133 drivers/clk/mmp/clk-of-pxa168.c {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock}, APBC_UART2 155 drivers/clk/mmp/clk-of-pxa168.c {PXA168_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock}, APBC_UART2 224 drivers/clk/mmp/clk-pxa168.c apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); APBC_UART2 229 drivers/clk/mmp/clk-pxa168.c apbc_base + APBC_UART2, 10, 0, &clk_lock);