APBC_PWM0         230 drivers/clk/mmp/clk-mmp2.c 				apbc_base + APBC_PWM0, 10, 0, &clk_lock);
APBC_PWM0         163 drivers/clk/mmp/clk-of-mmp2.c 	{MMP2_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x7, 0x3, 0x0, 0, &reset_lock},
APBC_PWM0         148 drivers/clk/mmp/clk-of-pxa168.c 	{PXA168_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
APBC_PWM0         146 drivers/clk/mmp/clk-of-pxa910.c 	{PXA910_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
APBC_PWM0         184 drivers/clk/mmp/clk-pxa168.c 				apbc_base + APBC_PWM0, 10, 0, &clk_lock);
APBC_PWM0         189 drivers/clk/mmp/clk-pxa910.c 				apbc_base + APBC_PWM0, 10, 0, &clk_lock);