I915_READ 41 drivers/gpu/drm/i915/display/icl_dsi.c return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) I915_READ 48 drivers/gpu/drm/i915/display/icl_dsi.c return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) I915_READ 111 drivers/gpu/drm/i915/display/icl_dsi.c if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) & I915_READ 160 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans)); I915_READ 214 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); I915_READ 221 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); I915_READ 228 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); I915_READ 236 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy)); I915_READ 244 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy)); I915_READ 254 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy)); I915_READ 272 drivers/gpu/drm/i915/display/icl_dsi.c dss_ctl1 = I915_READ(DSS_CTL1); I915_READ 292 drivers/gpu/drm/i915/display/icl_dsi.c dss_ctl2 = I915_READ(DSS_CTL2); I915_READ 354 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_DSI_IO_MODECTL(port)); I915_READ 383 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy)); I915_READ 387 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy)); I915_READ 397 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy)); I915_READ 401 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); I915_READ 408 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy)); I915_READ 413 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); I915_READ 431 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); I915_READ 434 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy)); I915_READ 445 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_CL_DW5(phy)); I915_READ 452 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); I915_READ 455 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); I915_READ 465 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); I915_READ 468 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); I915_READ 482 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(DDI_BUF_CTL(port)); I915_READ 486 drivers/gpu/drm/i915/display/icl_dsi.c if (wait_for_us(!(I915_READ(DDI_BUF_CTL(port)) & I915_READ 503 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_DSI_T_INIT_MASTER(port)); I915_READ 536 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(DPHY_TA_TIMING_PARAM(port)); I915_READ 542 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(DSI_TA_TIMING_PARAM(port)); I915_READ 552 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_DPHY_CHKN(phy)); I915_READ 567 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_DPCLKA_CFGCR0); I915_READ 583 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_DPCLKA_CFGCR0); I915_READ 602 drivers/gpu/drm/i915/display/icl_dsi.c val = I915_READ(ICL_DPCLKA_CFGCR0); I915_READ 636 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)); I915_READ 716 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans)); I915_READ 729 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); I915_READ 758 drivers/gpu/drm/i915/display/icl_dsi.c if (wait_for_us((I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)) & I915_READ 896 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(PIPECONF(dsi_trans)); I915_READ 933 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(DSI_HSTX_TO(dsi_trans)); I915_READ 941 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(DSI_LPRX_HOST_TO(dsi_trans)); I915_READ 949 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(DSI_TA_TO(dsi_trans)); I915_READ 1006 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(DSI_CMD_RXCTL(dsi_trans)); I915_READ 1076 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(PIPECONF(dsi_trans)); I915_READ 1110 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(DSI_LP_MSG(dsi_trans)); I915_READ 1115 drivers/gpu/drm/i915/display/icl_dsi.c if (wait_for_us((I915_READ(DSI_LP_MSG(dsi_trans)) & I915_READ 1124 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); I915_READ 1133 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans)); I915_READ 1149 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(DDI_BUF_CTL(port)); I915_READ 1153 drivers/gpu/drm/i915/display/icl_dsi.c if (wait_for_us((I915_READ(DDI_BUF_CTL(port)) & I915_READ 1182 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_DSI_IO_MODECTL(port)); I915_READ 1317 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); I915_READ 1333 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(PIPECONF(dsi_trans)); I915_READ 293 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(reg_eldv); I915_READ 299 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(reg_elda); I915_READ 304 drivers/gpu/drm/i915/display/intel_audio.c if (I915_READ(reg_edid) != *((const u32 *)eld + i)) I915_READ 319 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(G4X_AUD_VID_DID); I915_READ 326 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(G4X_AUD_CNTL_ST); I915_READ 344 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(G4X_AUD_VID_DID); I915_READ 356 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(G4X_AUD_CNTL_ST); I915_READ 366 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(G4X_AUD_CNTL_ST); I915_READ 390 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder)); I915_READ 404 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); I915_READ 431 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder)); I915_READ 454 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); I915_READ 484 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder)); I915_READ 494 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); I915_READ 519 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); I915_READ 532 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(cpu_transcoder)); I915_READ 542 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); I915_READ 581 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(aud_config); I915_READ 593 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(aud_cntrl_st2); I915_READ 646 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(aud_cntrl_st2); I915_READ 651 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(aud_cntl_st); I915_READ 661 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(aud_cntrl_st2); I915_READ 666 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(aud_config); I915_READ 890 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(HSW_AUD_CHICKENBIT); I915_READ 896 drivers/gpu/drm/i915/display/intel_audio.c tmp = I915_READ(HSW_AUD_CHICKENBIT); I915_READ 239 drivers/gpu/drm/i915/display/intel_cdclk.c tmp = I915_READ(IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? I915_READ 409 drivers/gpu/drm/i915/display/intel_cdclk.c u32 lcpll = I915_READ(LCPLL_CTL); I915_READ 414 drivers/gpu/drm/i915/display/intel_cdclk.c else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) I915_READ 522 drivers/gpu/drm/i915/display/intel_cdclk.c WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); I915_READ 689 drivers/gpu/drm/i915/display/intel_cdclk.c u32 lcpll = I915_READ(LCPLL_CTL); I915_READ 694 drivers/gpu/drm/i915/display/intel_cdclk.c else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) I915_READ 721 drivers/gpu/drm/i915/display/intel_cdclk.c if (WARN((I915_READ(LCPLL_CTL) & I915_READ 736 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(LCPLL_CTL); I915_READ 744 drivers/gpu/drm/i915/display/intel_cdclk.c if (wait_for_us(I915_READ(LCPLL_CTL) & I915_READ 748 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(LCPLL_CTL); I915_READ 771 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(LCPLL_CTL); I915_READ 775 drivers/gpu/drm/i915/display/intel_cdclk.c if (wait_for_us((I915_READ(LCPLL_CTL) & I915_READ 830 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(LCPLL1_CTL); I915_READ 837 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(DPLL_CTRL1); I915_READ 874 drivers/gpu/drm/i915/display/intel_cdclk.c cdctl = I915_READ(CDCLK_CTL); I915_READ 955 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(DPLL_CTRL1); I915_READ 970 drivers/gpu/drm/i915/display/intel_cdclk.c I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); I915_READ 983 drivers/gpu/drm/i915/display/intel_cdclk.c I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); I915_READ 1046 drivers/gpu/drm/i915/display/intel_cdclk.c cdclk_ctl = I915_READ(CDCLK_CTL); I915_READ 1091 drivers/gpu/drm/i915/display/intel_cdclk.c if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) I915_READ 1108 drivers/gpu/drm/i915/display/intel_cdclk.c cdctl = I915_READ(CDCLK_CTL); I915_READ 1247 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(BXT_DE_PLL_ENABLE); I915_READ 1254 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(BXT_DE_PLL_CTL); I915_READ 1271 drivers/gpu/drm/i915/display/intel_cdclk.c divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; I915_READ 1320 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(BXT_DE_PLL_CTL); I915_READ 1437 drivers/gpu/drm/i915/display/intel_cdclk.c cdctl = I915_READ(CDCLK_CTL); I915_READ 1533 drivers/gpu/drm/i915/display/intel_cdclk.c if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz) I915_READ 1540 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(BXT_DE_PLL_ENABLE); I915_READ 1563 drivers/gpu/drm/i915/display/intel_cdclk.c divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; I915_READ 1592 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(BXT_DE_PLL_ENABLE); I915_READ 1597 drivers/gpu/drm/i915/display/intel_cdclk.c if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1)) I915_READ 1615 drivers/gpu/drm/i915/display/intel_cdclk.c if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1)) I915_READ 1724 drivers/gpu/drm/i915/display/intel_cdclk.c cdctl = I915_READ(CDCLK_CTL); I915_READ 1887 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(SKL_DSSM); I915_READ 1903 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(BXT_DE_PLL_ENABLE); I915_READ 1917 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(CDCLK_CTL); I915_READ 1944 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(CDCLK_CTL); I915_READ 2636 drivers/gpu/drm/i915/display/intel_cdclk.c u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; I915_READ 2668 drivers/gpu/drm/i915/display/intel_cdclk.c if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) I915_READ 2720 drivers/gpu/drm/i915/display/intel_cdclk.c if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { I915_READ 2746 drivers/gpu/drm/i915/display/intel_cdclk.c return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; I915_READ 2761 drivers/gpu/drm/i915/display/intel_cdclk.c clkcfg = I915_READ(CLKCFG); I915_READ 432 drivers/gpu/drm/i915/display/intel_color.c val = I915_READ(PIPECONF(pipe)); I915_READ 445 drivers/gpu/drm/i915/display/intel_color.c val = I915_READ(PIPECONF(pipe)); I915_READ 51 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(ICL_PORT_COMP_DW3(phy)); I915_READ 84 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(ICL_PORT_COMP_DW1(phy)); I915_READ 97 drivers/gpu/drm/i915/display/intel_combo_phy.c u32 val = I915_READ(reg); I915_READ 130 drivers/gpu/drm/i915/display/intel_combo_phy.c return !(I915_READ(CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) && I915_READ 131 drivers/gpu/drm/i915/display/intel_combo_phy.c (I915_READ(CNL_PORT_COMP_DW0) & COMP_INIT); I915_READ 154 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(CHICKEN_MISC_2); I915_READ 161 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(CNL_PORT_COMP_DW0); I915_READ 165 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(CNL_PORT_CL1CM_DW5); I915_READ 177 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(CHICKEN_MISC_2); I915_READ 187 drivers/gpu/drm/i915/display/intel_combo_phy.c return I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT; I915_READ 189 drivers/gpu/drm/i915/display/intel_combo_phy.c return !(I915_READ(ICL_PHY_MISC(phy)) & I915_READ 191 drivers/gpu/drm/i915/display/intel_combo_phy.c (I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT); I915_READ 260 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(ICL_PORT_CL_DW10(phy)); I915_READ 321 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(ICL_PHY_MISC(phy)); I915_READ 331 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(ICL_PORT_COMP_DW8(phy)); I915_READ 336 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(ICL_PORT_COMP_DW0(phy)); I915_READ 340 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(ICL_PORT_CL_DW5(phy)); I915_READ 366 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(ICL_PHY_MISC(phy)); I915_READ 371 drivers/gpu/drm/i915/display/intel_combo_phy.c val = I915_READ(ICL_PORT_COMP_DW0(phy)); I915_READ 78 drivers/gpu/drm/i915/display/intel_crt.c val = I915_READ(adpa_reg); I915_READ 115 drivers/gpu/drm/i915/display/intel_crt.c tmp = I915_READ(crt->adpa_reg); I915_READ 437 drivers/gpu/drm/i915/display/intel_crt.c save_adpa = adpa = I915_READ(crt->adpa_reg); I915_READ 459 drivers/gpu/drm/i915/display/intel_crt.c adpa = I915_READ(crt->adpa_reg); I915_READ 493 drivers/gpu/drm/i915/display/intel_crt.c save_adpa = adpa = I915_READ(crt->adpa_reg); I915_READ 507 drivers/gpu/drm/i915/display/intel_crt.c adpa = I915_READ(crt->adpa_reg); I915_READ 556 drivers/gpu/drm/i915/display/intel_crt.c stat = I915_READ(PORT_HOTPLUG_STAT); I915_READ 701 drivers/gpu/drm/i915/display/intel_crt.c u32 vsync = I915_READ(vsync_reg); I915_READ 913 drivers/gpu/drm/i915/display/intel_crt.c adpa = I915_READ(crt->adpa_reg); I915_READ 964 drivers/gpu/drm/i915/display/intel_crt.c adpa = I915_READ(adpa_reg); I915_READ 976 drivers/gpu/drm/i915/display/intel_crt.c if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) I915_READ 1069 drivers/gpu/drm/i915/display/intel_crt.c dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; I915_READ 785 drivers/gpu/drm/i915/display/intel_ddi.c u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; I915_READ 806 drivers/gpu/drm/i915/display/intel_ddi.c u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; I915_READ 827 drivers/gpu/drm/i915/display/intel_ddi.c u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; I915_READ 992 drivers/gpu/drm/i915/display/intel_ddi.c if (I915_READ(reg) & DDI_BUF_IS_IDLE) I915_READ 1140 drivers/gpu/drm/i915/display/intel_ddi.c temp = I915_READ(FDI_RX_MISC(PIPE_A)); I915_READ 1148 drivers/gpu/drm/i915/display/intel_ddi.c temp = I915_READ(DP_TP_STATUS(PORT_E)); I915_READ 1167 drivers/gpu/drm/i915/display/intel_ddi.c temp = I915_READ(DDI_BUF_CTL(PORT_E)); I915_READ 1173 drivers/gpu/drm/i915/display/intel_ddi.c temp = I915_READ(DP_TP_CTL(PORT_E)); I915_READ 1182 drivers/gpu/drm/i915/display/intel_ddi.c temp = I915_READ(FDI_RX_MISC(PIPE_A)); I915_READ 1235 drivers/gpu/drm/i915/display/intel_ddi.c wrpll = I915_READ(reg); I915_READ 1244 drivers/gpu/drm/i915/display/intel_ddi.c if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT) I915_READ 1389 drivers/gpu/drm/i915/display/intel_ddi.c u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; I915_READ 1632 drivers/gpu/drm/i915/display/intel_ddi.c pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK; I915_READ 1756 drivers/gpu/drm/i915/display/intel_ddi.c temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); I915_READ 1857 drivers/gpu/drm/i915/display/intel_ddi.c u32 val = I915_READ(reg); I915_READ 1896 drivers/gpu/drm/i915/display/intel_ddi.c tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe)); I915_READ 1935 drivers/gpu/drm/i915/display/intel_ddi.c tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); I915_READ 1988 drivers/gpu/drm/i915/display/intel_ddi.c tmp = I915_READ(DDI_BUF_CTL(port)); I915_READ 1993 drivers/gpu/drm/i915/display/intel_ddi.c tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); I915_READ 2033 drivers/gpu/drm/i915/display/intel_ddi.c tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); I915_READ 2065 drivers/gpu/drm/i915/display/intel_ddi.c tmp = I915_READ(BXT_PHY_CTL(port)); I915_READ 2188 drivers/gpu/drm/i915/display/intel_ddi.c tmp = I915_READ(DISPIO_CR_TX_BMU_CR0); I915_READ 2350 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); I915_READ 2356 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(CNL_PORT_TX_DW2_LN0(port)); I915_READ 2368 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port)); I915_READ 2379 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); I915_READ 2386 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(CNL_PORT_TX_DW7_LN0(port)); I915_READ 2415 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(CNL_PORT_PCS_DW1_LN0(port)); I915_READ 2430 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port)); I915_READ 2441 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(CNL_PORT_CL1CM_DW5); I915_READ 2446 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); I915_READ 2454 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); I915_READ 2478 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); I915_READ 2487 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); I915_READ 2499 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); I915_READ 2509 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_PORT_TX_DW7_LN0(phy)); I915_READ 2541 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); I915_READ 2556 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); I915_READ 2567 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_PORT_CL_DW5(phy)); I915_READ 2572 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); I915_READ 2580 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); I915_READ 2606 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_TX1_LINK_PARAMS(ln, port)); I915_READ 2610 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_TX2_LINK_PARAMS(ln, port)); I915_READ 2617 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_TX1_SWINGCTRL(ln, port)); I915_READ 2623 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_TX2_SWINGCTRL(ln, port)); I915_READ 2632 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_TX1_DRVCTRL(ln, port)); I915_READ 2642 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_TX2_DRVCTRL(ln, port)); I915_READ 2661 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_CLKHUB(ln, port)); I915_READ 2671 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_TX1_DCC(ln, port)); I915_READ 2681 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_TX2_DCC(ln, port)); I915_READ 2694 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_TX1_PISO_READLOAD(ln, port)); I915_READ 2698 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_TX2_PISO_READLOAD(ln, port)); I915_READ 2799 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_DPCLKA_CFGCR0); I915_READ 2833 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_DPCLKA_CFGCR0); I915_READ 2893 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(ICL_DPCLKA_CFGCR0); I915_READ 2944 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DPCLKA_CFGCR0); I915_READ 2954 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DPCLKA_CFGCR0); I915_READ 2959 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DPLL_CTRL2); I915_READ 2986 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) | I915_READ 2989 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) | I915_READ 3008 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_DP_MODE(ln, port)); I915_READ 3017 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_MISC_SUS0(tc_port)); I915_READ 3040 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_DP_MODE(ln, port)); I915_READ 3049 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(MG_MISC_SUS0(tc_port)); I915_READ 3069 drivers/gpu/drm/i915/display/intel_ddi.c ln0 = I915_READ(MG_DP_MODE(0, port)); I915_READ 3070 drivers/gpu/drm/i915/display/intel_ddi.c ln1 = I915_READ(MG_DP_MODE(1, port)); I915_READ 3142 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DP_TP_CTL(port)); I915_READ 3161 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DP_TP_CTL(port)); I915_READ 3330 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DDI_BUF_CTL(port)); I915_READ 3337 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DP_TP_CTL(port)); I915_READ 3448 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(FDI_RX_CTL(PIPE_A)); I915_READ 3455 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(FDI_RX_MISC(PIPE_A)); I915_READ 3460 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(FDI_RX_CTL(PIPE_A)); I915_READ 3464 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(FDI_RX_CTL(PIPE_A)); I915_READ 3535 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(reg); I915_READ 3768 drivers/gpu/drm/i915/display/intel_ddi.c if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { I915_READ 3769 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DDI_BUF_CTL(port)); I915_READ 3776 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(DP_TP_CTL(port)); I915_READ 3814 drivers/gpu/drm/i915/display/intel_ddi.c return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) & I915_READ 3839 drivers/gpu/drm/i915/display/intel_ddi.c temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); I915_READ 4254 drivers/gpu/drm/i915/display/intel_ddi.c if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) I915_READ 4339 drivers/gpu/drm/i915/display/intel_ddi.c intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & I915_READ 4342 drivers/gpu/drm/i915/display/intel_ddi.c intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & I915_READ 497 drivers/gpu/drm/i915/display/intel_display.c I915_READ(CLKGATE_DIS_PSL(pipe)) | I915_READ 501 drivers/gpu/drm/i915/display/intel_display.c I915_READ(CLKGATE_DIS_PSL(pipe)) & I915_READ 512 drivers/gpu/drm/i915/display/intel_display.c I915_READ(CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); I915_READ 515 drivers/gpu/drm/i915/display/intel_display.c I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); I915_READ 1041 drivers/gpu/drm/i915/display/intel_display.c line1 = I915_READ(reg) & line_mask; I915_READ 1043 drivers/gpu/drm/i915/display/intel_display.c line2 = I915_READ(reg) & line_mask; I915_READ 1095 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(DPLL(pipe)); I915_READ 1127 drivers/gpu/drm/i915/display/intel_display.c u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); I915_READ 1130 drivers/gpu/drm/i915/display/intel_display.c u32 val = I915_READ(FDI_TX_CTL(pipe)); I915_READ 1146 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(FDI_RX_CTL(pipe)); I915_READ 1168 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(FDI_TX_CTL(pipe)); I915_READ 1178 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(FDI_RX_CTL(pipe)); I915_READ 1199 drivers/gpu/drm/i915/display/intel_display.c port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; I915_READ 1226 drivers/gpu/drm/i915/display/intel_display.c port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; I915_READ 1232 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(pp_reg); I915_READ 1258 drivers/gpu/drm/i915/display/intel_display.c u32 val = I915_READ(PIPECONF(cpu_transcoder)); I915_READ 1307 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(PCH_TRANSCONF(pipe)); I915_READ 1468 drivers/gpu/drm/i915/display/intel_display.c WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); I915_READ 1617 drivers/gpu/drm/i915/display/intel_display.c I915_READ(dpll_reg) & port_mask, expected_mask); I915_READ 1639 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(reg); I915_READ 1645 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(reg); I915_READ 1646 drivers/gpu/drm/i915/display/intel_display.c pipeconf_val = I915_READ(PIPECONF(pipe)); I915_READ 1687 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(TRANS_CHICKEN2(PIPE_A)); I915_READ 1692 drivers/gpu/drm/i915/display/intel_display.c pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); I915_READ 1720 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(reg); I915_READ 1730 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(reg); I915_READ 1740 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(LPT_TRANSCONF); I915_READ 1749 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(TRANS_CHICKEN2(PIPE_A)); I915_READ 1830 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(reg); I915_READ 1871 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(reg); I915_READ 3897 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(DSPCNTR(i9xx_plane)); I915_READ 4379 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(PIPE_CHICKEN(pipe)); I915_READ 4446 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4457 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4473 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | I915_READ 4493 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4497 drivers/gpu/drm/i915/display/intel_display.c I915_READ(reg); I915_READ 4502 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4510 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4525 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4539 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4545 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4555 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4591 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4601 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4615 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4630 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4640 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4657 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4668 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4683 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4693 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4724 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4733 drivers/gpu/drm/i915/display/intel_display.c I915_READ(FDI_RX_IIR(pipe))); I915_READ 4739 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4745 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4753 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4766 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4776 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4780 drivers/gpu/drm/i915/display/intel_display.c (I915_READ(reg) & FDI_RX_BIT_LOCK)) { I915_READ 4795 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4801 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4811 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4815 drivers/gpu/drm/i915/display/intel_display.c (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { I915_READ 4841 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4844 drivers/gpu/drm/i915/display/intel_display.c temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; I915_READ 4851 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4859 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4878 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4883 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4890 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4909 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4914 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4916 drivers/gpu/drm/i915/display/intel_display.c temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; I915_READ 4928 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4934 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 4944 drivers/gpu/drm/i915/display/intel_display.c temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; I915_READ 5078 drivers/gpu/drm/i915/display/intel_display.c if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) I915_READ 5115 drivers/gpu/drm/i915/display/intel_display.c I915_READ(HTOTAL(cpu_transcoder))); I915_READ 5117 drivers/gpu/drm/i915/display/intel_display.c I915_READ(HBLANK(cpu_transcoder))); I915_READ 5119 drivers/gpu/drm/i915/display/intel_display.c I915_READ(HSYNC(cpu_transcoder))); I915_READ 5122 drivers/gpu/drm/i915/display/intel_display.c I915_READ(VTOTAL(cpu_transcoder))); I915_READ 5124 drivers/gpu/drm/i915/display/intel_display.c I915_READ(VBLANK(cpu_transcoder))); I915_READ 5126 drivers/gpu/drm/i915/display/intel_display.c I915_READ(VSYNC(cpu_transcoder))); I915_READ 5128 drivers/gpu/drm/i915/display/intel_display.c I915_READ(VSYNCSHIFT(cpu_transcoder))); I915_READ 5135 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(SOUTH_CHICKEN1); I915_READ 5139 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); I915_READ 5140 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); I915_READ 5229 drivers/gpu/drm/i915/display/intel_display.c I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); I915_READ 5239 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(PCH_DPLL_SEL); I915_READ 5270 drivers/gpu/drm/i915/display/intel_display.c u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; I915_READ 5274 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 5319 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(dslreg); I915_READ 5321 drivers/gpu/drm/i915/display/intel_display.c if (wait_for(I915_READ(dslreg) != temp, 5)) { I915_READ 5322 drivers/gpu/drm/i915/display/intel_display.c if (wait_for(I915_READ(dslreg) != temp, 5)) I915_READ 6409 drivers/gpu/drm/i915/display/intel_display.c u32 val = I915_READ(CLKGATE_DIS_PSL(pipe)); I915_READ 6604 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); I915_READ 6611 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(PCH_DPLL_SEL); I915_READ 6670 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); I915_READ 6979 drivers/gpu/drm/i915/display/intel_display.c I915_READ(PFIT_CONTROL)); I915_READ 8178 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); I915_READ 8204 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(HTOTAL(cpu_transcoder)); I915_READ 8209 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(HBLANK(cpu_transcoder)); I915_READ 8215 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(HSYNC(cpu_transcoder)); I915_READ 8219 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(VTOTAL(cpu_transcoder)); I915_READ 8224 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(VBLANK(cpu_transcoder)); I915_READ 8230 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(VSYNC(cpu_transcoder)); I915_READ 8234 drivers/gpu/drm/i915/display/intel_display.c if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { I915_READ 8248 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(PIPESRC(crtc->pipe)); I915_READ 8289 drivers/gpu/drm/i915/display/intel_display.c pipeconf |= I915_READ(PIPECONF(crtc->pipe)) & PIPECONF_ENABLE; I915_READ 8544 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(PFIT_CONTROL); I915_READ 8558 drivers/gpu/drm/i915/display/intel_display.c pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); I915_READ 8618 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(DSPCNTR(i9xx_plane)); I915_READ 8639 drivers/gpu/drm/i915/display/intel_display.c offset = I915_READ(DSPOFFSET(i9xx_plane)); I915_READ 8640 drivers/gpu/drm/i915/display/intel_display.c base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000; I915_READ 8643 drivers/gpu/drm/i915/display/intel_display.c offset = I915_READ(DSPTILEOFF(i9xx_plane)); I915_READ 8645 drivers/gpu/drm/i915/display/intel_display.c offset = I915_READ(DSPLINOFF(i9xx_plane)); I915_READ 8646 drivers/gpu/drm/i915/display/intel_display.c base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000; I915_READ 8648 drivers/gpu/drm/i915/display/intel_display.c base = I915_READ(DSPADDR(i9xx_plane)); I915_READ 8652 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(PIPESRC(pipe)); I915_READ 8656 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(DSPSTRIDE(i9xx_plane)); I915_READ 8714 drivers/gpu/drm/i915/display/intel_display.c u32 tmp = I915_READ(PIPEMISC(crtc->pipe)); I915_READ 8756 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(DSPCNTR(i9xx_plane)); I915_READ 8786 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(PIPECONF(crtc->pipe)); I915_READ 8815 drivers/gpu/drm/i915/display/intel_display.c pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe)); I915_READ 8833 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(DPLL_MD(crtc->pipe)); I915_READ 8840 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(DPLL(crtc->pipe)); I915_READ 8850 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); I915_READ 8852 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); I915_READ 8853 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); I915_READ 8923 drivers/gpu/drm/i915/display/intel_display.c u32 temp = I915_READ(PCH_DPLL(i)); I915_READ 8943 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(PCH_DREF_CONTROL); I915_READ 9055 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(SOUTH_CHICKEN2); I915_READ 9059 drivers/gpu/drm/i915/display/intel_display.c if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & I915_READ 9063 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(SOUTH_CHICKEN2); I915_READ 9067 drivers/gpu/drm/i915/display/intel_display.c if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & I915_READ 9281 drivers/gpu/drm/i915/display/intel_display.c u32 fuse_strap = I915_READ(FUSE_STRAP); I915_READ 9282 drivers/gpu/drm/i915/display/intel_display.c u32 ctl = I915_READ(SPLL_CTL); I915_READ 9301 drivers/gpu/drm/i915/display/intel_display.c u32 fuse_strap = I915_READ(FUSE_STRAP); I915_READ 9302 drivers/gpu/drm/i915/display/intel_display.c u32 ctl = I915_READ(WRPLL_CTL(id)); I915_READ 9498 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(PIPEMISC(crtc->pipe)); I915_READ 9696 drivers/gpu/drm/i915/display/intel_display.c m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); I915_READ 9697 drivers/gpu/drm/i915/display/intel_display.c m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); I915_READ 9698 drivers/gpu/drm/i915/display/intel_display.c m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) I915_READ 9700 drivers/gpu/drm/i915/display/intel_display.c m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); I915_READ 9701 drivers/gpu/drm/i915/display/intel_display.c m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) I915_READ 9714 drivers/gpu/drm/i915/display/intel_display.c m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); I915_READ 9715 drivers/gpu/drm/i915/display/intel_display.c m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); I915_READ 9716 drivers/gpu/drm/i915/display/intel_display.c m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) I915_READ 9718 drivers/gpu/drm/i915/display/intel_display.c m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); I915_READ 9719 drivers/gpu/drm/i915/display/intel_display.c m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) I915_READ 9723 drivers/gpu/drm/i915/display/intel_display.c m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); I915_READ 9724 drivers/gpu/drm/i915/display/intel_display.c m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); I915_READ 9725 drivers/gpu/drm/i915/display/intel_display.c m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) I915_READ 9727 drivers/gpu/drm/i915/display/intel_display.c m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); I915_READ 9728 drivers/gpu/drm/i915/display/intel_display.c m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) I915_READ 9732 drivers/gpu/drm/i915/display/intel_display.c m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); I915_READ 9733 drivers/gpu/drm/i915/display/intel_display.c m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); I915_READ 9734 drivers/gpu/drm/i915/display/intel_display.c m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) I915_READ 9736 drivers/gpu/drm/i915/display/intel_display.c m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); I915_READ 9737 drivers/gpu/drm/i915/display/intel_display.c m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) I915_READ 9772 drivers/gpu/drm/i915/display/intel_display.c ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); I915_READ 9776 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); I915_READ 9777 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); I915_READ 9821 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(PLANE_CTL(pipe, plane_id)); I915_READ 9829 drivers/gpu/drm/i915/display/intel_display.c alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id)); I915_READ 9889 drivers/gpu/drm/i915/display/intel_display.c base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000; I915_READ 9892 drivers/gpu/drm/i915/display/intel_display.c offset = I915_READ(PLANE_OFFSET(pipe, plane_id)); I915_READ 9894 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(PLANE_SIZE(pipe, plane_id)); I915_READ 9898 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(PLANE_STRIDE(pipe, plane_id)); I915_READ 9925 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(PF_CTL(crtc->pipe)); I915_READ 9929 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); I915_READ 9930 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); I915_READ 9962 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(PIPECONF(crtc->pipe)); I915_READ 9989 drivers/gpu/drm/i915/display/intel_display.c pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe)); I915_READ 9994 drivers/gpu/drm/i915/display/intel_display.c if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { I915_READ 10000 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); I915_READ 10013 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(PCH_DPLL_SEL); I915_READ 10078 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); I915_READ 10097 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(ICL_DPCLKA_CFGCR0) & I915_READ 10102 drivers/gpu/drm/i915/display/intel_display.c u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; I915_READ 10155 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); I915_READ 10169 drivers/gpu/drm/i915/display/intel_display.c u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); I915_READ 10237 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(TRANS_DDI_FUNC_CTL(panel_transcoder)); I915_READ 10291 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); I915_READ 10336 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); I915_READ 10340 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(MIPI_CTRL(port)); I915_READ 10359 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); I915_READ 10389 drivers/gpu/drm/i915/display/intel_display.c (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { I915_READ 10392 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(FDI_RX_CTL(PIPE_A)); I915_READ 10443 drivers/gpu/drm/i915/display/intel_display.c pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe)); I915_READ 10445 drivers/gpu/drm/i915/display/intel_display.c pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe)); I915_READ 10448 drivers/gpu/drm/i915/display/intel_display.c u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe)); I915_READ 10477 drivers/gpu/drm/i915/display/intel_display.c pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE; I915_READ 10491 drivers/gpu/drm/i915/display/intel_display.c I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; I915_READ 10766 drivers/gpu/drm/i915/display/intel_display.c ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; I915_READ 11018 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(CURCNTR(plane->pipe)); I915_READ 11338 drivers/gpu/drm/i915/display/intel_display.c u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); I915_READ 15248 drivers/gpu/drm/i915/display/intel_display.c if ((I915_READ(DP_A) & DP_DETECTED) == 0) I915_READ 15251 drivers/gpu/drm/i915/display/intel_display.c if (IS_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) I915_READ 15266 drivers/gpu/drm/i915/display/intel_display.c I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) I915_READ 15270 drivers/gpu/drm/i915/display/intel_display.c if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) I915_READ 15296 drivers/gpu/drm/i915/display/intel_display.c u32 val = I915_READ(PP_CONTROL(pps_idx)); I915_READ 15374 drivers/gpu/drm/i915/display/intel_display.c found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; I915_READ 15381 drivers/gpu/drm/i915/display/intel_display.c found = I915_READ(SFUSE_STRAP); I915_READ 15414 drivers/gpu/drm/i915/display/intel_display.c if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { I915_READ 15419 drivers/gpu/drm/i915/display/intel_display.c if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) I915_READ 15423 drivers/gpu/drm/i915/display/intel_display.c if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) I915_READ 15426 drivers/gpu/drm/i915/display/intel_display.c if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) I915_READ 15429 drivers/gpu/drm/i915/display/intel_display.c if (I915_READ(PCH_DP_C) & DP_DETECTED) I915_READ 15432 drivers/gpu/drm/i915/display/intel_display.c if (I915_READ(PCH_DP_D) & DP_DETECTED) I915_READ 15457 drivers/gpu/drm/i915/display/intel_display.c if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) I915_READ 15459 drivers/gpu/drm/i915/display/intel_display.c if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) I915_READ 15464 drivers/gpu/drm/i915/display/intel_display.c if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) I915_READ 15466 drivers/gpu/drm/i915/display/intel_display.c if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) I915_READ 15475 drivers/gpu/drm/i915/display/intel_display.c if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) I915_READ 15477 drivers/gpu/drm/i915/display/intel_display.c if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) I915_READ 15493 drivers/gpu/drm/i915/display/intel_display.c if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { I915_READ 15507 drivers/gpu/drm/i915/display/intel_display.c if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { I915_READ 15512 drivers/gpu/drm/i915/display/intel_display.c if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { I915_READ 15522 drivers/gpu/drm/i915/display/intel_display.c if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) I915_READ 16060 drivers/gpu/drm/i915/display/intel_display.c I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK; I915_READ 16170 drivers/gpu/drm/i915/display/intel_display.c bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & I915_READ 16362 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE); I915_READ 16363 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE); I915_READ 16364 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE); I915_READ 16365 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE); I915_READ 16366 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE); I915_READ 16447 drivers/gpu/drm/i915/display/intel_display.c I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); I915_READ 16598 drivers/gpu/drm/i915/display/intel_display.c if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { I915_READ 16868 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | I915_READ 16877 drivers/gpu/drm/i915/display/intel_display.c I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); I915_READ 16884 drivers/gpu/drm/i915/display/intel_display.c u32 val = I915_READ(hdmi_reg); I915_READ 16902 drivers/gpu/drm/i915/display/intel_display.c u32 val = I915_READ(dp_reg); I915_READ 17235 drivers/gpu/drm/i915/display/intel_display.c error->power_well_driver = I915_READ(HSW_PWR_WELL_CTL2); I915_READ 17244 drivers/gpu/drm/i915/display/intel_display.c error->cursor[i].control = I915_READ(CURCNTR(i)); I915_READ 17245 drivers/gpu/drm/i915/display/intel_display.c error->cursor[i].position = I915_READ(CURPOS(i)); I915_READ 17246 drivers/gpu/drm/i915/display/intel_display.c error->cursor[i].base = I915_READ(CURBASE(i)); I915_READ 17248 drivers/gpu/drm/i915/display/intel_display.c error->plane[i].control = I915_READ(DSPCNTR(i)); I915_READ 17249 drivers/gpu/drm/i915/display/intel_display.c error->plane[i].stride = I915_READ(DSPSTRIDE(i)); I915_READ 17251 drivers/gpu/drm/i915/display/intel_display.c error->plane[i].size = I915_READ(DSPSIZE(i)); I915_READ 17252 drivers/gpu/drm/i915/display/intel_display.c error->plane[i].pos = I915_READ(DSPPOS(i)); I915_READ 17255 drivers/gpu/drm/i915/display/intel_display.c error->plane[i].addr = I915_READ(DSPADDR(i)); I915_READ 17257 drivers/gpu/drm/i915/display/intel_display.c error->plane[i].surface = I915_READ(DSPSURF(i)); I915_READ 17258 drivers/gpu/drm/i915/display/intel_display.c error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); I915_READ 17261 drivers/gpu/drm/i915/display/intel_display.c error->pipe[i].source = I915_READ(PIPESRC(i)); I915_READ 17264 drivers/gpu/drm/i915/display/intel_display.c error->pipe[i].stat = I915_READ(PIPESTAT(i)); I915_READ 17282 drivers/gpu/drm/i915/display/intel_display.c error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); I915_READ 17283 drivers/gpu/drm/i915/display/intel_display.c error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); I915_READ 17284 drivers/gpu/drm/i915/display/intel_display.c error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); I915_READ 17285 drivers/gpu/drm/i915/display/intel_display.c error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); I915_READ 17286 drivers/gpu/drm/i915/display/intel_display.c error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); I915_READ 17287 drivers/gpu/drm/i915/display/intel_display.c error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); I915_READ 17288 drivers/gpu/drm/i915/display/intel_display.c error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); I915_READ 339 drivers/gpu/drm/i915/display/intel_display_power.c ret = I915_READ(regs->bios) & req_mask ? 1 : 0; I915_READ 340 drivers/gpu/drm/i915/display/intel_display_power.c ret |= I915_READ(regs->driver) & req_mask ? 2 : 0; I915_READ 342 drivers/gpu/drm/i915/display/intel_display_power.c ret |= I915_READ(regs->kvmr) & req_mask ? 4 : 0; I915_READ 343 drivers/gpu/drm/i915/display/intel_display_power.c ret |= I915_READ(regs->debug) & req_mask ? 8 : 0; I915_READ 365 drivers/gpu/drm/i915/display/intel_display_power.c wait_for((disabled = !(I915_READ(regs->driver) & I915_READ 407 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(regs->driver); I915_READ 415 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(CNL_AUX_ANAOVRD1(pw_idx)); I915_READ 438 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(regs->driver); I915_READ 455 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(regs->driver); I915_READ 459 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(ICL_PORT_CL_DW12(phy)); I915_READ 474 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx)); I915_READ 490 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(ICL_PORT_CL_DW12(phy)); I915_READ 494 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(regs->driver); I915_READ 590 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(DP_AUX_CH_CTL(aux_ch)); I915_READ 623 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(regs->driver); I915_READ 633 drivers/gpu/drm/i915/display/intel_display_power.c val |= I915_READ(regs->bios); I915_READ 640 drivers/gpu/drm/i915/display/intel_display_power.c WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), I915_READ 642 drivers/gpu/drm/i915/display/intel_display_power.c WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, I915_READ 644 drivers/gpu/drm/i915/display/intel_display_power.c WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL2) & I915_READ 663 drivers/gpu/drm/i915/display/intel_display_power.c WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, I915_READ 690 drivers/gpu/drm/i915/display/intel_display_power.c v = I915_READ(DC_STATE_EN); I915_READ 731 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv); I915_READ 769 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(DC_STATE_EN); I915_READ 815 drivers/gpu/drm/i915/display/intel_display_power.c WARN_ONCE(!I915_READ(CSR_PROGRAM(0)), I915_READ 817 drivers/gpu/drm/i915/display/intel_display_power.c WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n"); I915_READ 818 drivers/gpu/drm/i915/display/intel_display_power.c WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n"); I915_READ 849 drivers/gpu/drm/i915/display/intel_display_power.c WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), I915_READ 864 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | I915_READ 872 drivers/gpu/drm/i915/display/intel_display_power.c WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, I915_READ 874 drivers/gpu/drm/i915/display/intel_display_power.c WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), I915_READ 888 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | I915_READ 900 drivers/gpu/drm/i915/display/intel_display_power.c u32 bios_req = I915_READ(regs->bios); I915_READ 904 drivers/gpu/drm/i915/display/intel_display_power.c u32 drv_req = I915_READ(regs->driver); I915_READ 954 drivers/gpu/drm/i915/display/intel_display_power.c return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0; I915_READ 959 drivers/gpu/drm/i915/display/intel_display_power.c u32 tmp = I915_READ(DBUF_CTL); I915_READ 1027 drivers/gpu/drm/i915/display/intel_display_power.c if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) I915_READ 1029 drivers/gpu/drm/i915/display/intel_display_power.c if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) I915_READ 1043 drivers/gpu/drm/i915/display/intel_display_power.c return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE && I915_READ 1044 drivers/gpu/drm/i915/display/intel_display_power.c I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; I915_READ 1150 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(DSPCLK_GATE_D); I915_READ 1181 drivers/gpu/drm/i915/display/intel_display_power.c u32 val = I915_READ(DPLL(pipe)); I915_READ 1267 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); I915_READ 1279 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); I915_READ 1341 drivers/gpu/drm/i915/display/intel_display_power.c (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) I915_READ 1387 drivers/gpu/drm/i915/display/intel_display_power.c I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask, I915_READ 4113 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(reg); I915_READ 4119 drivers/gpu/drm/i915/display/intel_display_power.c status = I915_READ(reg) & DBUF_POWER_STATE; I915_READ 4170 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST); I915_READ 4171 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST); I915_READ 4176 drivers/gpu/drm/i915/display/intel_display_power.c if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) || I915_READ 4177 drivers/gpu/drm/i915/display/intel_display_power.c !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)) I915_READ 4189 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST); I915_READ 4190 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST); I915_READ 4195 drivers/gpu/drm/i915/display/intel_display_power.c if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) || I915_READ 4196 drivers/gpu/drm/i915/display/intel_display_power.c (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)) I915_READ 4215 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(MBUS_ABOX_CTL); I915_READ 4226 drivers/gpu/drm/i915/display/intel_display_power.c u32 val = I915_READ(LCPLL_CTL); I915_READ 4253 drivers/gpu/drm/i915/display/intel_display_power.c I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL2), I915_READ 4255 drivers/gpu/drm/i915/display/intel_display_power.c I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, I915_READ 4257 drivers/gpu/drm/i915/display/intel_display_power.c I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, I915_READ 4259 drivers/gpu/drm/i915/display/intel_display_power.c I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, I915_READ 4261 drivers/gpu/drm/i915/display/intel_display_power.c I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, I915_READ 4263 drivers/gpu/drm/i915/display/intel_display_power.c I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, I915_READ 4266 drivers/gpu/drm/i915/display/intel_display_power.c I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, I915_READ 4268 drivers/gpu/drm/i915/display/intel_display_power.c I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, I915_READ 4270 drivers/gpu/drm/i915/display/intel_display_power.c I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, I915_READ 4272 drivers/gpu/drm/i915/display/intel_display_power.c I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, I915_READ 4287 drivers/gpu/drm/i915/display/intel_display_power.c return I915_READ(D_COMP_HSW); I915_READ 4289 drivers/gpu/drm/i915/display/intel_display_power.c return I915_READ(D_COMP_BDW); I915_READ 4319 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(LCPLL_CTL); I915_READ 4325 drivers/gpu/drm/i915/display/intel_display_power.c if (wait_for_us(I915_READ(LCPLL_CTL) & I915_READ 4329 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(LCPLL_CTL); I915_READ 4349 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(LCPLL_CTL); I915_READ 4364 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(LCPLL_CTL); I915_READ 4387 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(LCPLL_CTL); I915_READ 4395 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(LCPLL_CTL); I915_READ 4399 drivers/gpu/drm/i915/display/intel_display_power.c if (wait_for_us((I915_READ(LCPLL_CTL) & I915_READ 4440 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(SOUTH_DSPCLK_GATE_D); I915_READ 4459 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(SOUTH_DSPCLK_GATE_D); I915_READ 4479 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(reg); I915_READ 4765 drivers/gpu/drm/i915/display/intel_display_power.c u32 status = I915_READ(DPLL(PIPE_A)); I915_READ 4796 drivers/gpu/drm/i915/display/intel_display_power.c u32 status = I915_READ(DPIO_PHY_STATUS); I915_READ 4833 drivers/gpu/drm/i915/display/intel_display_power.c I915_READ(DPIO_CTL) & DPIO_CMNRST) I915_READ 280 drivers/gpu/drm/i915/display/intel_dp.c u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; I915_READ 734 drivers/gpu/drm/i915/display/intel_dp.c if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, I915_READ 745 drivers/gpu/drm/i915/display/intel_dp.c DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; I915_READ 755 drivers/gpu/drm/i915/display/intel_dp.c pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; I915_READ 906 drivers/gpu/drm/i915/display/intel_dp.c return I915_READ(PP_STATUS(pipe)) & PP_ON; I915_READ 912 drivers/gpu/drm/i915/display/intel_dp.c return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD; I915_READ 929 drivers/gpu/drm/i915/display/intel_dp.c u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) & I915_READ 1087 drivers/gpu/drm/i915/display/intel_dp.c pp_div = I915_READ(pp_div_reg); I915_READ 1110 drivers/gpu/drm/i915/display/intel_dp.c return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; I915_READ 1123 drivers/gpu/drm/i915/display/intel_dp.c return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; I915_READ 1137 drivers/gpu/drm/i915/display/intel_dp.c I915_READ(_pp_stat_reg(intel_dp)), I915_READ 1138 drivers/gpu/drm/i915/display/intel_dp.c I915_READ(_pp_ctrl_reg(intel_dp))); I915_READ 2389 drivers/gpu/drm/i915/display/intel_dp.c intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; I915_READ 2413 drivers/gpu/drm/i915/display/intel_dp.c trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); I915_READ 2466 drivers/gpu/drm/i915/display/intel_dp.c I915_READ(pp_stat_reg), I915_READ 2467 drivers/gpu/drm/i915/display/intel_dp.c I915_READ(pp_ctrl_reg)); I915_READ 2472 drivers/gpu/drm/i915/display/intel_dp.c I915_READ(pp_stat_reg), I915_READ 2473 drivers/gpu/drm/i915/display/intel_dp.c I915_READ(pp_ctrl_reg)); I915_READ 2534 drivers/gpu/drm/i915/display/intel_dp.c control = I915_READ(_pp_ctrl_reg(intel_dp)); I915_READ 2585 drivers/gpu/drm/i915/display/intel_dp.c I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); I915_READ 2649 drivers/gpu/drm/i915/display/intel_dp.c I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); I915_READ 2926 drivers/gpu/drm/i915/display/intel_dp.c bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; I915_READ 2937 drivers/gpu/drm/i915/display/intel_dp.c bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; I915_READ 3081 drivers/gpu/drm/i915/display/intel_dp.c u32 val = I915_READ(TRANS_DP_CTL(p)); I915_READ 3104 drivers/gpu/drm/i915/display/intel_dp.c val = I915_READ(dp_reg); I915_READ 3156 drivers/gpu/drm/i915/display/intel_dp.c tmp = I915_READ(intel_dp->output_reg); I915_READ 3161 drivers/gpu/drm/i915/display/intel_dp.c u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); I915_READ 3195 drivers/gpu/drm/i915/display/intel_dp.c if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) I915_READ 3318 drivers/gpu/drm/i915/display/intel_dp.c u32 temp = I915_READ(DP_TP_CTL(port)); I915_READ 3417 drivers/gpu/drm/i915/display/intel_dp.c u32 dp_reg = I915_READ(intel_dp->output_reg); I915_READ 4042 drivers/gpu/drm/i915/display/intel_dp.c val = I915_READ(DP_TP_CTL(port)); I915_READ 4072 drivers/gpu/drm/i915/display/intel_dp.c if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) I915_READ 5071 drivers/gpu/drm/i915/display/intel_dp.c return I915_READ(SDEISR) & bit; I915_READ 5094 drivers/gpu/drm/i915/display/intel_dp.c return I915_READ(SDEISR) & bit; I915_READ 5113 drivers/gpu/drm/i915/display/intel_dp.c return I915_READ(SDEISR) & bit; I915_READ 5136 drivers/gpu/drm/i915/display/intel_dp.c return I915_READ(PORT_HOTPLUG_STAT) & bit; I915_READ 5159 drivers/gpu/drm/i915/display/intel_dp.c return I915_READ(PORT_HOTPLUG_STAT) & bit; I915_READ 5167 drivers/gpu/drm/i915/display/intel_dp.c return I915_READ(DEISR) & DE_DP_A_HOTPLUG; I915_READ 5177 drivers/gpu/drm/i915/display/intel_dp.c return I915_READ(DEISR) & DE_DP_A_HOTPLUG; I915_READ 5187 drivers/gpu/drm/i915/display/intel_dp.c return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB; I915_READ 5197 drivers/gpu/drm/i915/display/intel_dp.c return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG; I915_READ 5222 drivers/gpu/drm/i915/display/intel_dp.c return I915_READ(GEN8_DE_PORT_ISR) & bit; I915_READ 5230 drivers/gpu/drm/i915/display/intel_dp.c return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port); I915_READ 6221 drivers/gpu/drm/i915/display/intel_dp.c intel_dp->DP = I915_READ(intel_dp->output_reg); I915_READ 6392 drivers/gpu/drm/i915/display/intel_dp.c pp_on = I915_READ(regs.pp_on); I915_READ 6393 drivers/gpu/drm/i915/display/intel_dp.c pp_off = I915_READ(regs.pp_off); I915_READ 6404 drivers/gpu/drm/i915/display/intel_dp.c pp_div = I915_READ(regs.pp_div); I915_READ 6609 drivers/gpu/drm/i915/display/intel_dp.c pp_ctl = I915_READ(regs.pp_ctrl); I915_READ 6616 drivers/gpu/drm/i915/display/intel_dp.c I915_READ(regs.pp_on), I915_READ 6617 drivers/gpu/drm/i915/display/intel_dp.c I915_READ(regs.pp_off), I915_READ 6619 drivers/gpu/drm/i915/display/intel_dp.c I915_READ(regs.pp_div) : I915_READ 6620 drivers/gpu/drm/i915/display/intel_dp.c (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK)); I915_READ 6707 drivers/gpu/drm/i915/display/intel_dp.c val = I915_READ(reg); I915_READ 7164 drivers/gpu/drm/i915/display/intel_dp.c intel_dp->DP = I915_READ(intel_dp->output_reg); I915_READ 7243 drivers/gpu/drm/i915/display/intel_dp.c u32 temp = I915_READ(PEG_BAND_GAP_DATA); I915_READ 329 drivers/gpu/drm/i915/display/intel_dp_mst.c temp = I915_READ(DP_TP_STATUS(port)); I915_READ 281 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); I915_READ 285 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch)); I915_READ 290 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch)); I915_READ 300 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch)); I915_READ 305 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); I915_READ 317 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) I915_READ 320 drivers/gpu/drm/i915/display/intel_dpio_phy.c if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & I915_READ 328 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { I915_READ 340 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 val = I915_READ(BXT_PORT_REF_DW6(phy)); I915_READ 376 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_P_CR_GT_DISP_PWRON); I915_READ 396 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); I915_READ 401 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); I915_READ 407 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); I915_READ 413 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PORT_CL2CM_DW6(phy)); I915_READ 435 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PORT_REF_DW8(phy)); I915_READ 443 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); I915_READ 455 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); I915_READ 459 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(BXT_P_CR_GT_DISP_PWRON); I915_READ 499 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(reg); I915_READ 602 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane)); I915_READ 630 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane)); I915_READ 380 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(PCH_DPLL(id)); I915_READ 382 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->fp0 = I915_READ(PCH_FP0(id)); I915_READ 383 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->fp1 = I915_READ(PCH_FP1(id)); I915_READ 406 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(PCH_DREF_CONTROL); I915_READ 525 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(WRPLL_CTL(id)); I915_READ 543 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(SPLL_CTL); I915_READ 568 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(WRPLL_CTL(id)); I915_READ 588 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(SPLL_CTL); I915_READ 990 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(DPLL_CTRL1); I915_READ 1016 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE); I915_READ 1036 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_READ(regs[id].ctl) & ~LCPLL_PLL_ENABLE); I915_READ 1062 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(regs[id].ctl); I915_READ 1066 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(DPLL_CTRL1); I915_READ 1071 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr1 = I915_READ(regs[id].cfgcr1); I915_READ 1072 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr2 = I915_READ(regs[id].cfgcr2); I915_READ 1100 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(regs[id].ctl); I915_READ 1104 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(DPLL_CTRL1); I915_READ 1516 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); I915_READ 1521 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); I915_READ 1525 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & I915_READ 1531 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch)); I915_READ 1536 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch)); I915_READ 1542 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp = I915_READ(BXT_PORT_PLL(phy, ch, 0)); I915_READ 1548 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp = I915_READ(BXT_PORT_PLL(phy, ch, 1)); I915_READ 1554 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp = I915_READ(BXT_PORT_PLL(phy, ch, 2)); I915_READ 1560 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp = I915_READ(BXT_PORT_PLL(phy, ch, 3)); I915_READ 1566 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp = I915_READ(BXT_PORT_PLL(phy, ch, 6)); I915_READ 1574 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp = I915_READ(BXT_PORT_PLL(phy, ch, 8)); I915_READ 1579 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp = I915_READ(BXT_PORT_PLL(phy, ch, 9)); I915_READ 1584 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp = I915_READ(BXT_PORT_PLL(phy, ch, 10)); I915_READ 1591 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch)); I915_READ 1599 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); I915_READ 1604 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK), I915_READ 1609 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp = I915_READ(BXT_PORT_TX_DW5_LN0(phy, ch)); I915_READ 1618 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch)); I915_READ 1631 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); I915_READ 1637 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); I915_READ 1641 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (wait_for_us(!(I915_READ(BXT_PORT_PLL_ENABLE(port)) & I915_READ 1667 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(BXT_PORT_PLL_ENABLE(port)); I915_READ 1671 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch)); I915_READ 1674 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch)); I915_READ 1677 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll0 = I915_READ(BXT_PORT_PLL(phy, ch, 0)); I915_READ 1680 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll1 = I915_READ(BXT_PORT_PLL(phy, ch, 1)); I915_READ 1683 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll2 = I915_READ(BXT_PORT_PLL(phy, ch, 2)); I915_READ 1686 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll3 = I915_READ(BXT_PORT_PLL(phy, ch, 3)); I915_READ 1689 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll6 = I915_READ(BXT_PORT_PLL(phy, ch, 6)); I915_READ 1694 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll8 = I915_READ(BXT_PORT_PLL(phy, ch, 8)); I915_READ 1697 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll9 = I915_READ(BXT_PORT_PLL(phy, ch, 9)); I915_READ 1700 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll10 = I915_READ(BXT_PORT_PLL(phy, ch, 10)); I915_READ 1709 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch)); I915_READ 1710 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) I915_READ 1713 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch))); I915_READ 2025 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(CNL_DPLL_ENABLE(id)); I915_READ 2063 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(CNL_DPLL_ENABLE(id)); I915_READ 2107 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(CNL_DPLL_ENABLE(id)); I915_READ 2125 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(CNL_DPLL_ENABLE(id)); I915_READ 2151 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(CNL_DPLL_ENABLE(id)); I915_READ 2155 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(CNL_DPLL_CFGCR0(id)); I915_READ 2160 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(id)); I915_READ 3057 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(MG_PLL_ENABLE(tc_port)); I915_READ 3061 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(tc_port)); I915_READ 3065 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_READ(MG_CLKTOP2_CORECLKCTL1(tc_port)); I915_READ 3070 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port)); I915_READ 3077 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(tc_port)); I915_READ 3078 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(tc_port)); I915_READ 3079 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_lf = I915_READ(MG_PLL_LF(tc_port)); I915_READ 3080 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(tc_port)); I915_READ 3081 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_ssc = I915_READ(MG_PLL_SSC(tc_port)); I915_READ 3083 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_bias = I915_READ(MG_PLL_BIAS(tc_port)); I915_READ 3085 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_READ(MG_PLL_TDC_COLDST_BIAS(tc_port)); I915_READ 3119 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(enable_reg); I915_READ 3124 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id)); I915_READ 3125 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id)); I915_READ 3128 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(4)); I915_READ 3129 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(4)); I915_READ 3131 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id)); I915_READ 3132 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id)); I915_READ 3201 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(MG_REFCLKIN_CTL(tc_port)); I915_READ 3206 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(MG_CLKTOP2_CORECLKCTL1(tc_port)); I915_READ 3211 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port)); I915_READ 3225 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(MG_PLL_BIAS(tc_port)); I915_READ 3230 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(MG_PLL_TDC_COLDST_BIAS(tc_port)); I915_READ 3244 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(enable_reg); I915_READ 3262 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(enable_reg); I915_READ 3357 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(enable_reg); I915_READ 3367 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(enable_reg); I915_READ 140 drivers/gpu/drm/i915/display/intel_dvo.c tmp = I915_READ(intel_dvo->dev.dvo_reg); I915_READ 155 drivers/gpu/drm/i915/display/intel_dvo.c tmp = I915_READ(intel_dvo->dev.dvo_reg); I915_READ 171 drivers/gpu/drm/i915/display/intel_dvo.c tmp = I915_READ(intel_dvo->dev.dvo_reg); I915_READ 193 drivers/gpu/drm/i915/display/intel_dvo.c u32 temp = I915_READ(dvo_reg); I915_READ 197 drivers/gpu/drm/i915/display/intel_dvo.c I915_READ(dvo_reg); I915_READ 207 drivers/gpu/drm/i915/display/intel_dvo.c u32 temp = I915_READ(dvo_reg); I915_READ 214 drivers/gpu/drm/i915/display/intel_dvo.c I915_READ(dvo_reg); I915_READ 289 drivers/gpu/drm/i915/display/intel_dvo.c dvo_val = I915_READ(dvo_reg) & I915_READ 484 drivers/gpu/drm/i915/display/intel_dvo.c dpll[pipe] = I915_READ(DPLL(pipe)); I915_READ 105 drivers/gpu/drm/i915/display/intel_fbc.c fbc_ctl = I915_READ(FBC_CONTROL); I915_READ 153 drivers/gpu/drm/i915/display/intel_fbc.c fbc_ctl = I915_READ(FBC_CONTROL); I915_READ 165 drivers/gpu/drm/i915/display/intel_fbc.c return I915_READ(FBC_CONTROL) & FBC_CTL_EN; I915_READ 195 drivers/gpu/drm/i915/display/intel_fbc.c dpfc_ctl = I915_READ(DPFC_CONTROL); I915_READ 204 drivers/gpu/drm/i915/display/intel_fbc.c return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; I915_READ 269 drivers/gpu/drm/i915/display/intel_fbc.c dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); I915_READ 278 drivers/gpu/drm/i915/display/intel_fbc.c return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; I915_READ 289 drivers/gpu/drm/i915/display/intel_fbc.c u32 val = I915_READ(CHICKEN_MISC_4); I915_READ 337 drivers/gpu/drm/i915/display/intel_fbc.c I915_READ(ILK_DISPLAY_CHICKEN1) | I915_READ 342 drivers/gpu/drm/i915/display/intel_fbc.c I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) | I915_READ 98 drivers/gpu/drm/i915/display/intel_fifo_underrun.c if ((I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) I915_READ 124 drivers/gpu/drm/i915/display/intel_fifo_underrun.c if (old && I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) I915_READ 146 drivers/gpu/drm/i915/display/intel_fifo_underrun.c u32 err_int = I915_READ(GEN7_ERR_INT); I915_READ 176 drivers/gpu/drm/i915/display/intel_fifo_underrun.c I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { I915_READ 212 drivers/gpu/drm/i915/display/intel_fifo_underrun.c u32 serr_int = I915_READ(SERR_INT); I915_READ 244 drivers/gpu/drm/i915/display/intel_fifo_underrun.c if (old && I915_READ(SERR_INT) & I915_READ 156 drivers/gpu/drm/i915/display/intel_gmbus.c val = I915_READ(DSPCLK_GATE_D); I915_READ 169 drivers/gpu/drm/i915/display/intel_gmbus.c val = I915_READ(SOUTH_DSPCLK_GATE_D); I915_READ 182 drivers/gpu/drm/i915/display/intel_gmbus.c val = I915_READ(GEN9_CLKGATE_DIS_4); I915_READ 114 drivers/gpu/drm/i915/display/intel_hdcp.c reg = I915_READ(PORT_HDCP_STATUS(port)); I915_READ 124 drivers/gpu/drm/i915/display/intel_hdcp.c reg = I915_READ(HDCP2_STATUS_DDI(port)); I915_READ 198 drivers/gpu/drm/i915/display/intel_hdcp.c val = I915_READ(HDCP_KEY_STATUS); I915_READ 207 drivers/gpu/drm/i915/display/intel_hdcp.c if (!(I915_READ(HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE)) I915_READ 483 drivers/gpu/drm/i915/display/intel_hdcp.c if (!(I915_READ(HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) { I915_READ 628 drivers/gpu/drm/i915/display/intel_hdcp.c an.reg[0] = I915_READ(PORT_HDCP_ANLO(port)); I915_READ 629 drivers/gpu/drm/i915/display/intel_hdcp.c an.reg[1] = I915_READ(PORT_HDCP_ANHI(port)); I915_READ 664 drivers/gpu/drm/i915/display/intel_hdcp.c if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) & I915_READ 695 drivers/gpu/drm/i915/display/intel_hdcp.c if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) & I915_READ 702 drivers/gpu/drm/i915/display/intel_hdcp.c I915_READ(PORT_HDCP_STATUS(port))); I915_READ 825 drivers/gpu/drm/i915/display/intel_hdcp.c I915_READ(PORT_HDCP_STATUS(port))); I915_READ 1498 drivers/gpu/drm/i915/display/intel_hdcp.c WARN_ON(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS); I915_READ 1509 drivers/gpu/drm/i915/display/intel_hdcp.c if (I915_READ(HDCP2_STATUS_DDI(port)) & LINK_AUTH_STATUS) { I915_READ 1512 drivers/gpu/drm/i915/display/intel_hdcp.c I915_READ(HDCP2_CTL_DDI(port)) | I915_READ 1531 drivers/gpu/drm/i915/display/intel_hdcp.c WARN_ON(!(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS)); I915_READ 1534 drivers/gpu/drm/i915/display/intel_hdcp.c I915_READ(HDCP2_CTL_DDI(port)) & ~CTL_LINK_ENCRYPTION_REQ); I915_READ 1648 drivers/gpu/drm/i915/display/intel_hdcp.c I915_READ(HDCP2_STATUS_DDI(port))); I915_READ 75 drivers/gpu/drm/i915/display/intel_hdmi.c WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, I915_READ 83 drivers/gpu/drm/i915/display/intel_hdmi.c WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) & I915_READ 211 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(VIDEO_DIP_CTL); I915_READ 248 drivers/gpu/drm/i915/display/intel_hdmi.c val = I915_READ(VIDEO_DIP_CTL); I915_READ 256 drivers/gpu/drm/i915/display/intel_hdmi.c *data++ = I915_READ(VIDEO_DIP_DATA); I915_READ 263 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(VIDEO_DIP_CTL); I915_READ 284 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); I915_READ 322 drivers/gpu/drm/i915/display/intel_hdmi.c val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); I915_READ 330 drivers/gpu/drm/i915/display/intel_hdmi.c *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe)); I915_READ 339 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); I915_READ 361 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); I915_READ 402 drivers/gpu/drm/i915/display/intel_hdmi.c val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); I915_READ 410 drivers/gpu/drm/i915/display/intel_hdmi.c *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe)); I915_READ 418 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); I915_READ 437 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); I915_READ 475 drivers/gpu/drm/i915/display/intel_hdmi.c val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe)); I915_READ 483 drivers/gpu/drm/i915/display/intel_hdmi.c *data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe)); I915_READ 491 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); I915_READ 515 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(ctl_reg); I915_READ 547 drivers/gpu/drm/i915/display/intel_hdmi.c val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder)); I915_READ 550 drivers/gpu/drm/i915/display/intel_hdmi.c *data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder, I915_READ 558 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); I915_READ 844 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); I915_READ 992 drivers/gpu/drm/i915/display/intel_hdmi.c crtc_state->infoframes.gcp = I915_READ(reg); I915_READ 1027 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); I915_READ 1085 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); I915_READ 1134 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); I915_READ 1190 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); I915_READ 1440 drivers/gpu/drm/i915/display/intel_hdmi.c scanline = I915_READ(PIPEDSL(intel_crtc->pipe)); I915_READ 1508 drivers/gpu/drm/i915/display/intel_hdmi.c if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) & I915_READ 1511 drivers/gpu/drm/i915/display/intel_hdmi.c I915_READ(PORT_HDCP_STATUS(port))); I915_READ 1788 drivers/gpu/drm/i915/display/intel_hdmi.c tmp = I915_READ(intel_hdmi->hdmi_reg); I915_READ 1864 drivers/gpu/drm/i915/display/intel_hdmi.c temp = I915_READ(intel_hdmi->hdmi_reg); I915_READ 1886 drivers/gpu/drm/i915/display/intel_hdmi.c temp = I915_READ(intel_hdmi->hdmi_reg); I915_READ 1938 drivers/gpu/drm/i915/display/intel_hdmi.c temp = I915_READ(intel_hdmi->hdmi_reg); I915_READ 1956 drivers/gpu/drm/i915/display/intel_hdmi.c I915_READ(TRANS_CHICKEN1(pipe)) | I915_READ 1974 drivers/gpu/drm/i915/display/intel_hdmi.c I915_READ(TRANS_CHICKEN1(pipe)) & I915_READ 2000 drivers/gpu/drm/i915/display/intel_hdmi.c temp = I915_READ(intel_hdmi->hdmi_reg); I915_READ 3124 drivers/gpu/drm/i915/display/intel_hdmi.c u32 temp = I915_READ(PEG_BAND_GAP_DATA); I915_READ 337 drivers/gpu/drm/i915/display/intel_lpe_audio.c audio_enable = I915_READ(VLV_AUD_PORT_EN_DBG(port)); I915_READ 88 drivers/gpu/drm/i915/display/intel_lvds.c val = I915_READ(lvds_reg); I915_READ 128 drivers/gpu/drm/i915/display/intel_lvds.c tmp = I915_READ(lvds_encoder->reg); I915_READ 146 drivers/gpu/drm/i915/display/intel_lvds.c tmp = I915_READ(PFIT_CONTROL); I915_READ 159 drivers/gpu/drm/i915/display/intel_lvds.c pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET; I915_READ 161 drivers/gpu/drm/i915/display/intel_lvds.c val = I915_READ(PP_ON_DELAYS(0)); I915_READ 166 drivers/gpu/drm/i915/display/intel_lvds.c val = I915_READ(PP_OFF_DELAYS(0)); I915_READ 170 drivers/gpu/drm/i915/display/intel_lvds.c val = I915_READ(PP_DIVISOR(0)); I915_READ 206 drivers/gpu/drm/i915/display/intel_lvds.c val = I915_READ(PP_CONTROL(0)); I915_READ 316 drivers/gpu/drm/i915/display/intel_lvds.c I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); I915_READ 318 drivers/gpu/drm/i915/display/intel_lvds.c I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON); I915_READ 334 drivers/gpu/drm/i915/display/intel_lvds.c I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON); I915_READ 338 drivers/gpu/drm/i915/display/intel_lvds.c I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); I915_READ 794 drivers/gpu/drm/i915/display/intel_lvds.c val = I915_READ(lvds_encoder->reg); I915_READ 845 drivers/gpu/drm/i915/display/intel_lvds.c lvds = I915_READ(lvds_reg); I915_READ 314 drivers/gpu/drm/i915/display/intel_overlay.c tmp = I915_READ(DOVSTA); I915_READ 451 drivers/gpu/drm/i915/display/intel_overlay.c if (!(I915_READ(GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { I915_READ 890 drivers/gpu/drm/i915/display/intel_overlay.c u32 pfit_control = I915_READ(PFIT_CONTROL); I915_READ 898 drivers/gpu/drm/i915/display/intel_overlay.c ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; I915_READ 901 drivers/gpu/drm/i915/display/intel_overlay.c ratio = I915_READ(PFIT_AUTO_RATIOS); I915_READ 903 drivers/gpu/drm/i915/display/intel_overlay.c ratio = I915_READ(PFIT_PGM_RATIOS); I915_READ 1246 drivers/gpu/drm/i915/display/intel_overlay.c attrs->gamma0 = I915_READ(OGAMC0); I915_READ 1247 drivers/gpu/drm/i915/display/intel_overlay.c attrs->gamma1 = I915_READ(OGAMC1); I915_READ 1248 drivers/gpu/drm/i915/display/intel_overlay.c attrs->gamma2 = I915_READ(OGAMC2); I915_READ 1249 drivers/gpu/drm/i915/display/intel_overlay.c attrs->gamma3 = I915_READ(OGAMC3); I915_READ 1250 drivers/gpu/drm/i915/display/intel_overlay.c attrs->gamma4 = I915_READ(OGAMC4); I915_READ 1251 drivers/gpu/drm/i915/display/intel_overlay.c attrs->gamma5 = I915_READ(OGAMC5); I915_READ 1433 drivers/gpu/drm/i915/display/intel_overlay.c error->dovsta = I915_READ(DOVSTA); I915_READ 1434 drivers/gpu/drm/i915/display/intel_overlay.c error->isr = I915_READ(GEN2_ISR); I915_READ 540 drivers/gpu/drm/i915/display/intel_panel.c return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; I915_READ 547 drivers/gpu/drm/i915/display/intel_panel.c return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; I915_READ 556 drivers/gpu/drm/i915/display/intel_panel.c val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; I915_READ 575 drivers/gpu/drm/i915/display/intel_panel.c return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; I915_READ 591 drivers/gpu/drm/i915/display/intel_panel.c return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller)); I915_READ 608 drivers/gpu/drm/i915/display/intel_panel.c u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; I915_READ 618 drivers/gpu/drm/i915/display/intel_panel.c tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; I915_READ 646 drivers/gpu/drm/i915/display/intel_panel.c tmp = I915_READ(BLC_PWM_CTL) & ~mask; I915_READ 657 drivers/gpu/drm/i915/display/intel_panel.c tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; I915_READ 745 drivers/gpu/drm/i915/display/intel_panel.c tmp = I915_READ(BLC_PWM_CPU_CTL2); I915_READ 751 drivers/gpu/drm/i915/display/intel_panel.c tmp = I915_READ(BLC_PWM_PCH_CTL1); I915_READ 763 drivers/gpu/drm/i915/display/intel_panel.c tmp = I915_READ(BLC_PWM_CPU_CTL2); I915_READ 766 drivers/gpu/drm/i915/display/intel_panel.c tmp = I915_READ(BLC_PWM_PCH_CTL1); I915_READ 782 drivers/gpu/drm/i915/display/intel_panel.c tmp = I915_READ(BLC_PWM_CTL2); I915_READ 795 drivers/gpu/drm/i915/display/intel_panel.c tmp = I915_READ(VLV_BLC_PWM_CTL2(pipe)); I915_READ 808 drivers/gpu/drm/i915/display/intel_panel.c tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); I915_READ 813 drivers/gpu/drm/i915/display/intel_panel.c val = I915_READ(UTIL_PIN_CTL); I915_READ 828 drivers/gpu/drm/i915/display/intel_panel.c tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); I915_READ 882 drivers/gpu/drm/i915/display/intel_panel.c pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); I915_READ 890 drivers/gpu/drm/i915/display/intel_panel.c schicken = I915_READ(SOUTH_CHICKEN2); I915_READ 897 drivers/gpu/drm/i915/display/intel_panel.c schicken = I915_READ(SOUTH_CHICKEN1); I915_READ 933 drivers/gpu/drm/i915/display/intel_panel.c cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); I915_READ 940 drivers/gpu/drm/i915/display/intel_panel.c pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); I915_READ 978 drivers/gpu/drm/i915/display/intel_panel.c ctl = I915_READ(BLC_PWM_CTL); I915_READ 1018 drivers/gpu/drm/i915/display/intel_panel.c ctl2 = I915_READ(BLC_PWM_CTL2); I915_READ 1053 drivers/gpu/drm/i915/display/intel_panel.c ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe)); I915_READ 1085 drivers/gpu/drm/i915/display/intel_panel.c val = I915_READ(UTIL_PIN_CTL); I915_READ 1099 drivers/gpu/drm/i915/display/intel_panel.c pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); I915_READ 1130 drivers/gpu/drm/i915/display/intel_panel.c pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); I915_READ 1496 drivers/gpu/drm/i915/display/intel_panel.c if ((I915_READ(CBR1_VLV) & CBR_PWM_CLOCK_MUX_SELECT) == 0) { I915_READ 1576 drivers/gpu/drm/i915/display/intel_panel.c alt = I915_READ(SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY; I915_READ 1578 drivers/gpu/drm/i915/display/intel_panel.c alt = I915_READ(SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY; I915_READ 1581 drivers/gpu/drm/i915/display/intel_panel.c pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); I915_READ 1584 drivers/gpu/drm/i915/display/intel_panel.c pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2); I915_READ 1587 drivers/gpu/drm/i915/display/intel_panel.c cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); I915_READ 1629 drivers/gpu/drm/i915/display/intel_panel.c pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); I915_READ 1632 drivers/gpu/drm/i915/display/intel_panel.c pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2); I915_READ 1648 drivers/gpu/drm/i915/display/intel_panel.c cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); I915_READ 1661 drivers/gpu/drm/i915/display/intel_panel.c ctl = I915_READ(BLC_PWM_CTL); I915_READ 1700 drivers/gpu/drm/i915/display/intel_panel.c ctl2 = I915_READ(BLC_PWM_CTL2); I915_READ 1704 drivers/gpu/drm/i915/display/intel_panel.c ctl = I915_READ(BLC_PWM_CTL); I915_READ 1737 drivers/gpu/drm/i915/display/intel_panel.c ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe)); I915_READ 1740 drivers/gpu/drm/i915/display/intel_panel.c ctl = I915_READ(VLV_BLC_PWM_CTL(pipe)); I915_READ 1770 drivers/gpu/drm/i915/display/intel_panel.c pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); I915_READ 1774 drivers/gpu/drm/i915/display/intel_panel.c val = I915_READ(UTIL_PIN_CTL); I915_READ 1781 drivers/gpu/drm/i915/display/intel_panel.c I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller)); I915_READ 1815 drivers/gpu/drm/i915/display/intel_panel.c pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); I915_READ 1819 drivers/gpu/drm/i915/display/intel_panel.c I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller)); I915_READ 175 drivers/gpu/drm/i915/display/intel_pipe_crc.c u32 tmp = I915_READ(PORT_DFT2_G4X); I915_READ 240 drivers/gpu/drm/i915/display/intel_pipe_crc.c u32 tmp = I915_READ(PORT_DFT2_G4X); I915_READ 216 drivers/gpu/drm/i915/display/intel_psr.c u32 val = I915_READ(PSR_EVENT(cpu_transcoder)); I915_READ 226 drivers/gpu/drm/i915/display/intel_psr.c mask |= I915_READ(EDP_PSR_IMR); I915_READ 494 drivers/gpu/drm/i915/display/intel_psr.c val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK; I915_READ 652 drivers/gpu/drm/i915/display/intel_psr.c WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); I915_READ 653 drivers/gpu/drm/i915/display/intel_psr.c WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); I915_READ 702 drivers/gpu/drm/i915/display/intel_psr.c u32 chicken = I915_READ(reg); I915_READ 786 drivers/gpu/drm/i915/display/intel_psr.c WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); I915_READ 787 drivers/gpu/drm/i915/display/intel_psr.c WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); I915_READ 792 drivers/gpu/drm/i915/display/intel_psr.c val = I915_READ(EDP_PSR2_CTL); I915_READ 796 drivers/gpu/drm/i915/display/intel_psr.c val = I915_READ(EDP_PSR_CTL); I915_READ 1234 drivers/gpu/drm/i915/display/intel_psr.c val = I915_READ(EDP_PSR_IIR); I915_READ 234 drivers/gpu/drm/i915/display/intel_sdvo.c cval = I915_READ(GEN3_SDVOC); I915_READ 236 drivers/gpu/drm/i915/display/intel_sdvo.c bval = I915_READ(GEN3_SDVOB); I915_READ 1521 drivers/gpu/drm/i915/display/intel_sdvo.c sdvox = I915_READ(intel_sdvo->sdvo_reg); I915_READ 1567 drivers/gpu/drm/i915/display/intel_sdvo.c val = I915_READ(sdvo_reg); I915_READ 1610 drivers/gpu/drm/i915/display/intel_sdvo.c sdvox = I915_READ(intel_sdvo->sdvo_reg); I915_READ 1737 drivers/gpu/drm/i915/display/intel_sdvo.c temp = I915_READ(intel_sdvo->sdvo_reg); I915_READ 1794 drivers/gpu/drm/i915/display/intel_sdvo.c temp = I915_READ(intel_sdvo->sdvo_reg); I915_READ 711 drivers/gpu/drm/i915/display/intel_sprite.c ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; I915_READ 1025 drivers/gpu/drm/i915/display/intel_sprite.c ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE; I915_READ 1251 drivers/gpu/drm/i915/display/intel_sprite.c ret = I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE; I915_READ 1499 drivers/gpu/drm/i915/display/intel_sprite.c ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE; I915_READ 910 drivers/gpu/drm/i915/display/intel_tv.c u32 tmp = I915_READ(TV_CTL); I915_READ 929 drivers/gpu/drm/i915/display/intel_tv.c I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE); I915_READ 940 drivers/gpu/drm/i915/display/intel_tv.c I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE); I915_READ 1099 drivers/gpu/drm/i915/display/intel_tv.c tv_ctl = I915_READ(TV_CTL); I915_READ 1100 drivers/gpu/drm/i915/display/intel_tv.c hctl1 = I915_READ(TV_H_CTL_1); I915_READ 1101 drivers/gpu/drm/i915/display/intel_tv.c hctl3 = I915_READ(TV_H_CTL_3); I915_READ 1102 drivers/gpu/drm/i915/display/intel_tv.c vctl1 = I915_READ(TV_V_CTL_1); I915_READ 1103 drivers/gpu/drm/i915/display/intel_tv.c vctl2 = I915_READ(TV_V_CTL_2); I915_READ 1138 drivers/gpu/drm/i915/display/intel_tv.c tmp = I915_READ(TV_WIN_POS); I915_READ 1142 drivers/gpu/drm/i915/display/intel_tv.c tmp = I915_READ(TV_WIN_SIZE); I915_READ 1438 drivers/gpu/drm/i915/display/intel_tv.c tv_ctl = I915_READ(TV_CTL); I915_READ 1560 drivers/gpu/drm/i915/display/intel_tv.c I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE); I915_READ 1585 drivers/gpu/drm/i915/display/intel_tv.c save_tv_dac = tv_dac = I915_READ(TV_DAC); I915_READ 1586 drivers/gpu/drm/i915/display/intel_tv.c save_tv_ctl = tv_ctl = I915_READ(TV_CTL); I915_READ 1619 drivers/gpu/drm/i915/display/intel_tv.c tv_dac = I915_READ(TV_DAC); I915_READ 1874 drivers/gpu/drm/i915/display/intel_tv.c if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED) I915_READ 1886 drivers/gpu/drm/i915/display/intel_tv.c save_tv_dac = I915_READ(TV_DAC); I915_READ 1889 drivers/gpu/drm/i915/display/intel_tv.c tv_dac_on = I915_READ(TV_DAC); I915_READ 1892 drivers/gpu/drm/i915/display/intel_tv.c tv_dac_off = I915_READ(TV_DAC); I915_READ 957 drivers/gpu/drm/i915/display/intel_vdsc.c dss_ctl1_val = I915_READ(dss_ctl1_reg); I915_READ 962 drivers/gpu/drm/i915/display/intel_vdsc.c dss_ctl2_val = I915_READ(dss_ctl2_reg); I915_READ 115 drivers/gpu/drm/i915/display/vlv_dsi.c u32 val = I915_READ(reg); I915_READ 230 drivers/gpu/drm/i915/display/vlv_dsi.c if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) I915_READ 332 drivers/gpu/drm/i915/display/vlv_dsi.c tmp = I915_READ(MIPI_CTRL(port)); I915_READ 337 drivers/gpu/drm/i915/display/vlv_dsi.c tmp = I915_READ(MIPI_CTRL(PORT_A)); I915_READ 343 drivers/gpu/drm/i915/display/vlv_dsi.c tmp = I915_READ(MIPI_CTRL(port)); I915_READ 344 drivers/gpu/drm/i915/display/vlv_dsi.c if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) I915_READ 361 drivers/gpu/drm/i915/display/vlv_dsi.c !(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY); I915_READ 382 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(MIPI_CTRL(PORT_A)); I915_READ 387 drivers/gpu/drm/i915/display/vlv_dsi.c if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) { I915_READ 388 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(MIPI_DEVICE_READY(port)); I915_READ 395 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(MIPI_DEVICE_READY(port)); I915_READ 406 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(MIPI_DEVICE_READY(port)); I915_READ 412 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(MIPI_DEVICE_READY(port)); I915_READ 417 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(MIPI_CTRL(port)); I915_READ 449 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(BXT_MIPI_PORT_CTRL(port)); I915_READ 456 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(MIPI_DEVICE_READY(port)); I915_READ 492 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(MIPI_PORT_CTRL(PORT_A)); I915_READ 525 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(MIPI_DEVICE_READY(port)); I915_READ 554 drivers/gpu/drm/i915/display/vlv_dsi.c tmp = I915_READ(MIPI_CTRL(PORT_A)); I915_READ 567 drivers/gpu/drm/i915/display/vlv_dsi.c tmp = I915_READ(MIPI_CTRL(port)); I915_READ 614 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(port_ctrl); I915_READ 635 drivers/gpu/drm/i915/display/vlv_dsi.c temp = I915_READ(MIPI_CTRL(port)); I915_READ 642 drivers/gpu/drm/i915/display/vlv_dsi.c temp = I915_READ(VLV_CHICKEN_3); I915_READ 655 drivers/gpu/drm/i915/display/vlv_dsi.c temp = I915_READ(port_ctrl); I915_READ 693 drivers/gpu/drm/i915/display/vlv_dsi.c temp = I915_READ(port_ctrl); I915_READ 775 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(BXT_P_CR_GT_DISP_PWRON); I915_READ 788 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(DSPCLK_GATE_D); I915_READ 922 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(BXT_P_CR_GT_DISP_PWRON); I915_READ 934 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(DSPCLK_GATE_D); I915_READ 983 drivers/gpu/drm/i915/display/vlv_dsi.c bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; I915_READ 992 drivers/gpu/drm/i915/display/vlv_dsi.c enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; I915_READ 996 drivers/gpu/drm/i915/display/vlv_dsi.c u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port)); I915_READ 1003 drivers/gpu/drm/i915/display/vlv_dsi.c if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) I915_READ 1007 drivers/gpu/drm/i915/display/vlv_dsi.c u32 tmp = I915_READ(MIPI_CTRL(port)); I915_READ 1055 drivers/gpu/drm/i915/display/vlv_dsi.c if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) I915_READ 1059 drivers/gpu/drm/i915/display/vlv_dsi.c fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; I915_READ 1071 drivers/gpu/drm/i915/display/vlv_dsi.c I915_READ(BXT_MIPI_TRANS_HACTIVE(port)); I915_READ 1073 drivers/gpu/drm/i915/display/vlv_dsi.c I915_READ(BXT_MIPI_TRANS_VACTIVE(port)); I915_READ 1075 drivers/gpu/drm/i915/display/vlv_dsi.c I915_READ(BXT_MIPI_TRANS_VTOTAL(port)); I915_READ 1078 drivers/gpu/drm/i915/display/vlv_dsi.c hfp = I915_READ(MIPI_HFP_COUNT(port)); I915_READ 1084 drivers/gpu/drm/i915/display/vlv_dsi.c hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port)); I915_READ 1085 drivers/gpu/drm/i915/display/vlv_dsi.c hbp = I915_READ(MIPI_HBP_COUNT(port)); I915_READ 1102 drivers/gpu/drm/i915/display/vlv_dsi.c vfp = I915_READ(MIPI_VFP_COUNT(port)); I915_READ 1103 drivers/gpu/drm/i915/display/vlv_dsi.c vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port)); I915_READ 1104 drivers/gpu/drm/i915/display/vlv_dsi.c vbp = I915_READ(MIPI_VBP_COUNT(port)); I915_READ 1342 drivers/gpu/drm/i915/display/vlv_dsi.c tmp = I915_READ(MIPI_CTRL(PORT_A)); I915_READ 1348 drivers/gpu/drm/i915/display/vlv_dsi.c tmp = I915_READ(MIPI_CTRL(port)); I915_READ 1355 drivers/gpu/drm/i915/display/vlv_dsi.c tmp = I915_READ(MIPI_CTRL(port)); I915_READ 1526 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(MIPI_DSI_FUNC_PRG(port)); I915_READ 1590 drivers/gpu/drm/i915/display/vlv_dsi.c val = I915_READ(DSPCNTR(plane->i9xx_plane)); I915_READ 204 drivers/gpu/drm/i915/display/vlv_dsi_pll.c val = I915_READ(BXT_DSI_PLL_ENABLE); I915_READ 218 drivers/gpu/drm/i915/display/vlv_dsi_pll.c val = I915_READ(BXT_DSI_PLL_CTL); I915_READ 241 drivers/gpu/drm/i915/display/vlv_dsi_pll.c val = I915_READ(BXT_DSI_PLL_ENABLE); I915_READ 328 drivers/gpu/drm/i915/display/vlv_dsi_pll.c config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL); I915_READ 346 drivers/gpu/drm/i915/display/vlv_dsi_pll.c temp = I915_READ(MIPI_CTRL(port)); I915_READ 415 drivers/gpu/drm/i915/display/vlv_dsi_pll.c tmp = I915_READ(BXT_MIPI_CLOCK_CTL); I915_READ 525 drivers/gpu/drm/i915/display/vlv_dsi_pll.c val = I915_READ(BXT_DSI_PLL_ENABLE); I915_READ 547 drivers/gpu/drm/i915/display/vlv_dsi_pll.c tmp = I915_READ(BXT_MIPI_CLOCK_CTL); I915_READ 554 drivers/gpu/drm/i915/display/vlv_dsi_pll.c tmp = I915_READ(MIPIO_TXESC_CLK_DIV1); I915_READ 558 drivers/gpu/drm/i915/display/vlv_dsi_pll.c tmp = I915_READ(MIPIO_TXESC_CLK_DIV2); I915_READ 87 drivers/gpu/drm/i915/gem/i915_gem_stolen.c ggtt_start = I915_READ(PGTBL_CTL); I915_READ 165 drivers/gpu/drm/i915/gem/i915_gem_stolen.c u32 reg_val = I915_READ(IS_GM45(dev_priv) ? I915_READ 196 drivers/gpu/drm/i915/gem/i915_gem_stolen.c u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED); I915_READ 228 drivers/gpu/drm/i915/gem/i915_gem_stolen.c u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED); I915_READ 256 drivers/gpu/drm/i915/gem/i915_gem_stolen.c u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED); I915_READ 282 drivers/gpu/drm/i915/gem/i915_gem_stolen.c u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED); I915_READ 314 drivers/gpu/drm/i915/gem/i915_gem_stolen.c u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED); I915_READ 180 drivers/gpu/drm/i915/gt/intel_engine_cs.c cxt_size = I915_READ(GEN7_CXT_SIZE); I915_READ 184 drivers/gpu/drm/i915/gt/intel_engine_cs.c cxt_size = I915_READ(CXT_SIZE); I915_READ 199 drivers/gpu/drm/i915/gt/intel_engine_cs.c cxt_size = I915_READ(CXT_SIZE) + 1; I915_READ 1657 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); I915_READ 395 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN8_DE_PIPE_IMR(pipe))); I915_READ 398 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN8_DE_PIPE_IIR(pipe))); I915_READ 401 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN8_DE_PIPE_IER(pipe))); I915_READ 407 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN8_DE_PORT_IMR)); I915_READ 409 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN8_DE_PORT_IIR)); I915_READ 411 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN8_DE_PORT_IER)); I915_READ 414 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN8_DE_MISC_IMR)); I915_READ 416 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN8_DE_MISC_IIR)); I915_READ 418 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN8_DE_MISC_IER)); I915_READ 421 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN8_PCU_IMR)); I915_READ 423 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN8_PCU_IIR)); I915_READ 425 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN8_PCU_IER)); I915_READ 441 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN8_MASTER_IRQ)); I915_READ 444 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(VLV_IER)); I915_READ 446 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(VLV_IIR)); I915_READ 448 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(VLV_IIR_RW)); I915_READ 450 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(VLV_IMR)); I915_READ 465 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(PIPESTAT(pipe))); I915_READ 472 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(PORT_HOTPLUG_EN)); I915_READ 474 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(VLV_DPFLIPSTAT)); I915_READ 476 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(DPINVGTT)); I915_READ 481 drivers/gpu/drm/i915/i915_debugfs.c i, I915_READ(GEN8_GT_IMR(i))); I915_READ 483 drivers/gpu/drm/i915/i915_debugfs.c i, I915_READ(GEN8_GT_IIR(i))); I915_READ 485 drivers/gpu/drm/i915/i915_debugfs.c i, I915_READ(GEN8_GT_IER(i))); I915_READ 489 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN8_PCU_IMR)); I915_READ 491 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN8_PCU_IIR)); I915_READ 493 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN8_PCU_IER)); I915_READ 496 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN11_GFX_MSTR_IRQ)); I915_READ 499 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN11_RENDER_COPY_INTR_ENABLE)); I915_READ 501 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN11_VCS_VECS_INTR_ENABLE)); I915_READ 503 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN11_GUC_SG_INTR_ENABLE)); I915_READ 505 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE)); I915_READ 507 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE)); I915_READ 509 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE)); I915_READ 512 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN11_DISPLAY_INT_CTL)); I915_READ 517 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN8_MASTER_IRQ)); I915_READ 521 drivers/gpu/drm/i915/i915_debugfs.c i, I915_READ(GEN8_GT_IMR(i))); I915_READ 523 drivers/gpu/drm/i915/i915_debugfs.c i, I915_READ(GEN8_GT_IIR(i))); I915_READ 525 drivers/gpu/drm/i915/i915_debugfs.c i, I915_READ(GEN8_GT_IER(i))); I915_READ 531 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(VLV_IER)); I915_READ 533 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(VLV_IIR)); I915_READ 535 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(VLV_IIR_RW)); I915_READ 537 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(VLV_IMR)); I915_READ 553 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(PIPESTAT(pipe))); I915_READ 558 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(VLV_MASTER_IER)); I915_READ 561 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GTIER)); I915_READ 563 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GTIIR)); I915_READ 565 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GTIMR)); I915_READ 568 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN6_PMIER)); I915_READ 570 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN6_PMIIR)); I915_READ 572 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN6_PMIMR)); I915_READ 575 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(PORT_HOTPLUG_EN)); I915_READ 577 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(VLV_DPFLIPSTAT)); I915_READ 579 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(DPINVGTT)); I915_READ 583 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN2_IER)); I915_READ 585 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN2_IIR)); I915_READ 587 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN2_IMR)); I915_READ 591 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(PIPESTAT(pipe))); I915_READ 594 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(DEIER)); I915_READ 596 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(DEIIR)); I915_READ 598 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(DEIMR)); I915_READ 600 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(SDEIER)); I915_READ 602 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(SDEIIR)); I915_READ 604 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(SDEIMR)); I915_READ 606 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GTIER)); I915_READ 608 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GTIIR)); I915_READ 610 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GTIMR)); I915_READ 615 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN11_RCS0_RSVD_INTR_MASK)); I915_READ 617 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN11_BCS_RSVD_INTR_MASK)); I915_READ 619 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN11_VCS0_VCS1_INTR_MASK)); I915_READ 621 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN11_VCS2_VCS3_INTR_MASK)); I915_READ 623 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN11_VECS0_VECS1_INTR_MASK)); I915_READ 625 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN11_GUC_SG_INTR_MASK)); I915_READ 627 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK)); I915_READ 629 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK)); I915_READ 631 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN11_GUNIT_CSME_INTR_MASK)); I915_READ 794 drivers/gpu/drm/i915/i915_debugfs.c rpmodectl = I915_READ(GEN6_RP_CONTROL); I915_READ 839 drivers/gpu/drm/i915/i915_debugfs.c rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); I915_READ 841 drivers/gpu/drm/i915/i915_debugfs.c rp_state_cap = I915_READ(BXT_RP_STATE_CAP); I915_READ 842 drivers/gpu/drm/i915/i915_debugfs.c gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); I915_READ 844 drivers/gpu/drm/i915/i915_debugfs.c rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); I915_READ 845 drivers/gpu/drm/i915/i915_debugfs.c gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); I915_READ 851 drivers/gpu/drm/i915/i915_debugfs.c reqf = I915_READ(GEN6_RPNSWREQ); I915_READ 863 drivers/gpu/drm/i915/i915_debugfs.c rpmodectl = I915_READ(GEN6_RP_CONTROL); I915_READ 864 drivers/gpu/drm/i915/i915_debugfs.c rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); I915_READ 865 drivers/gpu/drm/i915/i915_debugfs.c rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); I915_READ 867 drivers/gpu/drm/i915/i915_debugfs.c rpstat = I915_READ(GEN6_RPSTAT1); I915_READ 868 drivers/gpu/drm/i915/i915_debugfs.c rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; I915_READ 869 drivers/gpu/drm/i915/i915_debugfs.c rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; I915_READ 870 drivers/gpu/drm/i915/i915_debugfs.c rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; I915_READ 871 drivers/gpu/drm/i915/i915_debugfs.c rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; I915_READ 872 drivers/gpu/drm/i915/i915_debugfs.c rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; I915_READ 873 drivers/gpu/drm/i915/i915_debugfs.c rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; I915_READ 880 drivers/gpu/drm/i915/i915_debugfs.c pm_ier = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE); I915_READ 881 drivers/gpu/drm/i915/i915_debugfs.c pm_imr = I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK); I915_READ 889 drivers/gpu/drm/i915/i915_debugfs.c pm_ier = I915_READ(GEN8_GT_IER(2)); I915_READ 890 drivers/gpu/drm/i915/i915_debugfs.c pm_imr = I915_READ(GEN8_GT_IMR(2)); I915_READ 891 drivers/gpu/drm/i915/i915_debugfs.c pm_isr = I915_READ(GEN8_GT_ISR(2)); I915_READ 892 drivers/gpu/drm/i915/i915_debugfs.c pm_iir = I915_READ(GEN8_GT_IIR(2)); I915_READ 894 drivers/gpu/drm/i915/i915_debugfs.c pm_ier = I915_READ(GEN6_PMIER); I915_READ 895 drivers/gpu/drm/i915/i915_debugfs.c pm_imr = I915_READ(GEN6_PMIMR); I915_READ 896 drivers/gpu/drm/i915/i915_debugfs.c pm_isr = I915_READ(GEN6_PMISR); I915_READ 897 drivers/gpu/drm/i915/i915_debugfs.c pm_iir = I915_READ(GEN6_PMIIR); I915_READ 899 drivers/gpu/drm/i915/i915_debugfs.c pm_mask = I915_READ(GEN6_PMINTRMSK); I915_READ 1163 drivers/gpu/drm/i915/i915_debugfs.c title, I915_READ(reg), I915_READ 1172 drivers/gpu/drm/i915/i915_debugfs.c pw_status = I915_READ(VLV_GTLC_PW_STATUS); I915_READ 1173 drivers/gpu/drm/i915/i915_debugfs.c rcctl1 = I915_READ(GEN6_RC_CONTROL); I915_READ 1198 drivers/gpu/drm/i915/i915_debugfs.c rcctl1 = I915_READ(GEN6_RC_CONTROL); I915_READ 1200 drivers/gpu/drm/i915/i915_debugfs.c gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); I915_READ 1201 drivers/gpu/drm/i915/i915_debugfs.c gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); I915_READ 1326 drivers/gpu/drm/i915/i915_debugfs.c mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK; I915_READ 1328 drivers/gpu/drm/i915/i915_debugfs.c mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; I915_READ 1330 drivers/gpu/drm/i915/i915_debugfs.c mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK; I915_READ 1332 drivers/gpu/drm/i915/i915_debugfs.c mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK; I915_READ 1334 drivers/gpu/drm/i915/i915_debugfs.c mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING | I915_READ 1368 drivers/gpu/drm/i915/i915_debugfs.c reg = I915_READ(ILK_DPFC_CONTROL); I915_READ 1399 drivers/gpu/drm/i915/i915_debugfs.c if (I915_READ(IPS_CTL) & IPS_ENABLE) I915_READ 1421 drivers/gpu/drm/i915/i915_debugfs.c sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; I915_READ 1424 drivers/gpu/drm/i915/i915_debugfs.c sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; I915_READ 1426 drivers/gpu/drm/i915/i915_debugfs.c sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; I915_READ 1428 drivers/gpu/drm/i915/i915_debugfs.c sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; I915_READ 1430 drivers/gpu/drm/i915/i915_debugfs.c sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; I915_READ 1727 drivers/gpu/drm/i915/i915_debugfs.c I915_READ(GEN6_RPSTAT1)); I915_READ 1802 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2)); I915_READ 1820 drivers/gpu/drm/i915/i915_debugfs.c u32 tmp = I915_READ(GUC_STATUS); I915_READ 1833 drivers/gpu/drm/i915/i915_debugfs.c i, I915_READ(SOFT_SCRATCH(i))); I915_READ 2136 drivers/gpu/drm/i915/i915_debugfs.c val = I915_READ(EDP_PSR2_STATUS); I915_READ 2152 drivers/gpu/drm/i915/i915_debugfs.c val = I915_READ(EDP_PSR_STATUS); I915_READ 2195 drivers/gpu/drm/i915/i915_debugfs.c val = I915_READ(EDP_PSR2_CTL); I915_READ 2198 drivers/gpu/drm/i915/i915_debugfs.c val = I915_READ(EDP_PSR_CTL); I915_READ 2211 drivers/gpu/drm/i915/i915_debugfs.c val = I915_READ(EDP_PSR_PERF_CNT) & EDP_PSR_PERF_CNT_MASK; I915_READ 2230 drivers/gpu/drm/i915/i915_debugfs.c su_frames_val[frame / 3] = I915_READ(PSR2_SU_STATUS(frame)); I915_READ 2303 drivers/gpu/drm/i915/i915_debugfs.c power = I915_READ(MCH_SECP_NRG_STTS); I915_READ 2406 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg)); I915_READ 2408 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(dc6_reg)); I915_READ 2411 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); I915_READ 2412 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); I915_READ 2413 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); I915_READ 3691 drivers/gpu/drm/i915/i915_debugfs.c snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); I915_READ 3715 drivers/gpu/drm/i915/i915_debugfs.c snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); I915_READ 3736 drivers/gpu/drm/i915/i915_debugfs.c sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); I915_READ 3737 drivers/gpu/drm/i915/i915_debugfs.c sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); I915_READ 3738 drivers/gpu/drm/i915/i915_debugfs.c sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); I915_READ 3739 drivers/gpu/drm/i915/i915_debugfs.c sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); I915_READ 3776 drivers/gpu/drm/i915/i915_debugfs.c s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) & I915_READ 3778 drivers/gpu/drm/i915/i915_debugfs.c eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s)); I915_READ 3779 drivers/gpu/drm/i915/i915_debugfs.c eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s)); I915_READ 3826 drivers/gpu/drm/i915/i915_debugfs.c s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); I915_READ 3827 drivers/gpu/drm/i915/i915_debugfs.c eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); I915_READ 3828 drivers/gpu/drm/i915/i915_debugfs.c eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); I915_READ 3876 drivers/gpu/drm/i915/i915_debugfs.c u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); I915_READ 884 drivers/gpu/drm/i915/i915_drv.c val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN); I915_READ 889 drivers/gpu/drm/i915/i915_drv.c val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN); I915_READ 928 drivers/gpu/drm/i915/i915_drv.c val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN); I915_READ 959 drivers/gpu/drm/i915/i915_drv.c val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); I915_READ 1063 drivers/gpu/drm/i915/i915_drv.c val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0); I915_READ 1085 drivers/gpu/drm/i915/i915_drv.c val = I915_READ(BXT_D_CR_DRP0_DUNIT(i)); I915_READ 2251 drivers/gpu/drm/i915/i915_drv.c s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); I915_READ 2252 drivers/gpu/drm/i915/i915_drv.c s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); I915_READ 2253 drivers/gpu/drm/i915/i915_drv.c s->arb_mode = I915_READ(ARB_MODE); I915_READ 2254 drivers/gpu/drm/i915/i915_drv.c s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); I915_READ 2255 drivers/gpu/drm/i915/i915_drv.c s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); I915_READ 2258 drivers/gpu/drm/i915/i915_drv.c s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i)); I915_READ 2260 drivers/gpu/drm/i915/i915_drv.c s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); I915_READ 2261 drivers/gpu/drm/i915/i915_drv.c s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); I915_READ 2263 drivers/gpu/drm/i915/i915_drv.c s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); I915_READ 2264 drivers/gpu/drm/i915/i915_drv.c s->ecochk = I915_READ(GAM_ECOCHK); I915_READ 2265 drivers/gpu/drm/i915/i915_drv.c s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); I915_READ 2266 drivers/gpu/drm/i915/i915_drv.c s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); I915_READ 2268 drivers/gpu/drm/i915/i915_drv.c s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); I915_READ 2271 drivers/gpu/drm/i915/i915_drv.c s->g3dctl = I915_READ(VLV_G3DCTL); I915_READ 2272 drivers/gpu/drm/i915/i915_drv.c s->gsckgctl = I915_READ(VLV_GSCKGCTL); I915_READ 2273 drivers/gpu/drm/i915/i915_drv.c s->mbctl = I915_READ(GEN6_MBCTL); I915_READ 2276 drivers/gpu/drm/i915/i915_drv.c s->ucgctl1 = I915_READ(GEN6_UCGCTL1); I915_READ 2277 drivers/gpu/drm/i915/i915_drv.c s->ucgctl3 = I915_READ(GEN6_UCGCTL3); I915_READ 2278 drivers/gpu/drm/i915/i915_drv.c s->rcgctl1 = I915_READ(GEN6_RCGCTL1); I915_READ 2279 drivers/gpu/drm/i915/i915_drv.c s->rcgctl2 = I915_READ(GEN6_RCGCTL2); I915_READ 2280 drivers/gpu/drm/i915/i915_drv.c s->rstctl = I915_READ(GEN6_RSTCTL); I915_READ 2281 drivers/gpu/drm/i915/i915_drv.c s->misccpctl = I915_READ(GEN7_MISCCPCTL); I915_READ 2284 drivers/gpu/drm/i915/i915_drv.c s->gfxpause = I915_READ(GEN6_GFXPAUSE); I915_READ 2285 drivers/gpu/drm/i915/i915_drv.c s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); I915_READ 2286 drivers/gpu/drm/i915/i915_drv.c s->rpdeuc = I915_READ(GEN6_RPDEUC); I915_READ 2287 drivers/gpu/drm/i915/i915_drv.c s->ecobus = I915_READ(ECOBUS); I915_READ 2288 drivers/gpu/drm/i915/i915_drv.c s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); I915_READ 2289 drivers/gpu/drm/i915/i915_drv.c s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); I915_READ 2290 drivers/gpu/drm/i915/i915_drv.c s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); I915_READ 2291 drivers/gpu/drm/i915/i915_drv.c s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); I915_READ 2292 drivers/gpu/drm/i915/i915_drv.c s->rcedata = I915_READ(VLV_RCEDATA); I915_READ 2293 drivers/gpu/drm/i915/i915_drv.c s->spare2gh = I915_READ(VLV_SPAREG2H); I915_READ 2296 drivers/gpu/drm/i915/i915_drv.c s->gt_imr = I915_READ(GTIMR); I915_READ 2297 drivers/gpu/drm/i915/i915_drv.c s->gt_ier = I915_READ(GTIER); I915_READ 2298 drivers/gpu/drm/i915/i915_drv.c s->pm_imr = I915_READ(GEN6_PMIMR); I915_READ 2299 drivers/gpu/drm/i915/i915_drv.c s->pm_ier = I915_READ(GEN6_PMIER); I915_READ 2302 drivers/gpu/drm/i915/i915_drv.c s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i)); I915_READ 2305 drivers/gpu/drm/i915/i915_drv.c s->tilectl = I915_READ(TILECTL); I915_READ 2306 drivers/gpu/drm/i915/i915_drv.c s->gt_fifoctl = I915_READ(GTFIFOCTL); I915_READ 2307 drivers/gpu/drm/i915/i915_drv.c s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); I915_READ 2308 drivers/gpu/drm/i915/i915_drv.c s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); I915_READ 2309 drivers/gpu/drm/i915/i915_drv.c s->pmwgicz = I915_READ(VLV_PMWGICZ); I915_READ 2312 drivers/gpu/drm/i915/i915_drv.c s->gu_ctl0 = I915_READ(VLV_GU_CTL0); I915_READ 2313 drivers/gpu/drm/i915/i915_drv.c s->gu_ctl1 = I915_READ(VLV_GU_CTL1); I915_READ 2314 drivers/gpu/drm/i915/i915_drv.c s->pcbr = I915_READ(VLV_PCBR); I915_READ 2315 drivers/gpu/drm/i915/i915_drv.c s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); I915_READ 2397 drivers/gpu/drm/i915/i915_drv.c val = I915_READ(VLV_GTLC_WAKE_CTRL); I915_READ 2402 drivers/gpu/drm/i915/i915_drv.c val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); I915_READ 2445 drivers/gpu/drm/i915/i915_drv.c val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); I915_READ 2461 drivers/gpu/drm/i915/i915_drv.c I915_READ(VLV_GTLC_SURVIVABILITY_REG)); I915_READ 2472 drivers/gpu/drm/i915/i915_drv.c val = I915_READ(VLV_GTLC_WAKE_CTRL); I915_READ 2512 drivers/gpu/drm/i915/i915_drv.c if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) I915_READ 2531 drivers/gpu/drm/i915/i915_drv.c WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); I915_READ 1072 drivers/gpu/drm/i915/i915_gpu_error.c ee->fault_reg = I915_READ(GEN12_RING_FAULT_REG); I915_READ 1074 drivers/gpu/drm/i915/i915_gpu_error.c ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG); I915_READ 1135 drivers/gpu/drm/i915/i915_gpu_error.c ee->hws = I915_READ(mmio); I915_READ 1160 drivers/gpu/drm/i915/i915_gpu_error.c I915_READ(GEN8_RING_PDP_UDW(base, i)); I915_READ 1163 drivers/gpu/drm/i915/i915_gpu_error.c I915_READ(GEN8_RING_PDP_LDW(base, i)); I915_READ 273 drivers/gpu/drm/i915/i915_irq.c val = I915_READ(PORT_HOTPLUG_EN); I915_READ 375 drivers/gpu/drm/i915/i915_irq.c WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); I915_READ 524 drivers/gpu/drm/i915/i915_irq.c old_val = I915_READ(GEN8_DE_PORT_IMR); I915_READ 578 drivers/gpu/drm/i915/i915_irq.c u32 sdeimr = I915_READ(SDEIMR); I915_READ 831 drivers/gpu/drm/i915/i915_irq.c return I915_READ(PIPE_FRMCOUNT_G4X(pipe)); I915_READ 1120 drivers/gpu/drm/i915/i915_irq.c ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT); I915_READ 1121 drivers/gpu/drm/i915/i915_irq.c ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT); I915_READ 1297 drivers/gpu/drm/i915/i915_irq.c misccpctl = I915_READ(GEN7_MISCCPCTL); I915_READ 1312 drivers/gpu/drm/i915/i915_irq.c error_status = I915_READ(reg); I915_READ 1618 drivers/gpu/drm/i915/i915_irq.c I915_READ(PIPE_CRC_RES_1_IVB(pipe)), I915_READ 1626 drivers/gpu/drm/i915/i915_irq.c I915_READ(PIPE_CRC_RES_1_IVB(pipe)), I915_READ 1627 drivers/gpu/drm/i915/i915_irq.c I915_READ(PIPE_CRC_RES_2_IVB(pipe)), I915_READ 1628 drivers/gpu/drm/i915/i915_irq.c I915_READ(PIPE_CRC_RES_3_IVB(pipe)), I915_READ 1629 drivers/gpu/drm/i915/i915_irq.c I915_READ(PIPE_CRC_RES_4_IVB(pipe)), I915_READ 1630 drivers/gpu/drm/i915/i915_irq.c I915_READ(PIPE_CRC_RES_5_IVB(pipe))); I915_READ 1639 drivers/gpu/drm/i915/i915_irq.c res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); I915_READ 1644 drivers/gpu/drm/i915/i915_irq.c res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); I915_READ 1649 drivers/gpu/drm/i915/i915_irq.c I915_READ(PIPE_CRC_RES_RED(pipe)), I915_READ 1650 drivers/gpu/drm/i915/i915_irq.c I915_READ(PIPE_CRC_RES_GREEN(pipe)), I915_READ 1651 drivers/gpu/drm/i915/i915_irq.c I915_READ(PIPE_CRC_RES_BLUE(pipe)), I915_READ 1761 drivers/gpu/drm/i915/i915_irq.c pipe_stats[pipe] = I915_READ(reg) & status_mask; I915_READ 1891 drivers/gpu/drm/i915/i915_irq.c u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask; I915_READ 1902 drivers/gpu/drm/i915/i915_irq.c I915_READ(PORT_HOTPLUG_STAT)); I915_READ 1957 drivers/gpu/drm/i915/i915_irq.c gt_iir = I915_READ(GTIIR); I915_READ 1958 drivers/gpu/drm/i915/i915_irq.c pm_iir = I915_READ(GEN6_PMIIR); I915_READ 1959 drivers/gpu/drm/i915/i915_irq.c iir = I915_READ(VLV_IIR); I915_READ 1980 drivers/gpu/drm/i915/i915_irq.c ier = I915_READ(VLV_IER); I915_READ 2043 drivers/gpu/drm/i915/i915_irq.c master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; I915_READ 2044 drivers/gpu/drm/i915/i915_irq.c iir = I915_READ(VLV_IIR); I915_READ 2065 drivers/gpu/drm/i915/i915_irq.c ier = I915_READ(VLV_IER); I915_READ 2117 drivers/gpu/drm/i915/i915_irq.c dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); I915_READ 2170 drivers/gpu/drm/i915/i915_irq.c I915_READ(FDI_RX_IIR(pipe))); I915_READ 2187 drivers/gpu/drm/i915/i915_irq.c u32 err_int = I915_READ(GEN7_ERR_INT); I915_READ 2210 drivers/gpu/drm/i915/i915_irq.c u32 serr_int = I915_READ(SERR_INT); I915_READ 2253 drivers/gpu/drm/i915/i915_irq.c I915_READ(FDI_RX_IIR(pipe))); I915_READ 2277 drivers/gpu/drm/i915/i915_irq.c dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI); I915_READ 2289 drivers/gpu/drm/i915/i915_irq.c dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC); I915_READ 2314 drivers/gpu/drm/i915/i915_irq.c dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI); I915_READ 2326 drivers/gpu/drm/i915/i915_irq.c dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC); I915_READ 2352 drivers/gpu/drm/i915/i915_irq.c dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); I915_READ 2363 drivers/gpu/drm/i915/i915_irq.c dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2); I915_READ 2384 drivers/gpu/drm/i915/i915_irq.c dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); I915_READ 2425 drivers/gpu/drm/i915/i915_irq.c u32 pch_iir = I915_READ(SDEIIR); I915_READ 2453 drivers/gpu/drm/i915/i915_irq.c u32 psr_iir = I915_READ(EDP_PSR_IIR); I915_READ 2472 drivers/gpu/drm/i915/i915_irq.c u32 pch_iir = I915_READ(SDEIIR); I915_READ 2502 drivers/gpu/drm/i915/i915_irq.c de_ier = I915_READ(DEIER); I915_READ 2511 drivers/gpu/drm/i915/i915_irq.c sde_ier = I915_READ(SDEIER); I915_READ 2517 drivers/gpu/drm/i915/i915_irq.c gt_iir = I915_READ(GTIIR); I915_READ 2527 drivers/gpu/drm/i915/i915_irq.c de_iir = I915_READ(DEIIR); I915_READ 2538 drivers/gpu/drm/i915/i915_irq.c u32 pm_iir = I915_READ(GEN6_PMIIR); I915_READ 2562 drivers/gpu/drm/i915/i915_irq.c dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); I915_READ 2591 drivers/gpu/drm/i915/i915_irq.c dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL); I915_READ 2601 drivers/gpu/drm/i915/i915_irq.c dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL); I915_READ 2658 drivers/gpu/drm/i915/i915_irq.c u32 psr_iir = I915_READ(EDP_PSR_IIR); I915_READ 2677 drivers/gpu/drm/i915/i915_irq.c iir = I915_READ(GEN8_DE_MISC_IIR); I915_READ 2688 drivers/gpu/drm/i915/i915_irq.c iir = I915_READ(GEN11_DE_HPD_IIR); I915_READ 2699 drivers/gpu/drm/i915/i915_irq.c iir = I915_READ(GEN8_DE_PORT_IIR); I915_READ 2746 drivers/gpu/drm/i915/i915_irq.c iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); I915_READ 2778 drivers/gpu/drm/i915/i915_irq.c iir = I915_READ(SDEIIR); I915_READ 3159 drivers/gpu/drm/i915/i915_irq.c WARN_ON(I915_READ(SDEIER) != 0); I915_READ 3174 drivers/gpu/drm/i915/i915_irq.c intel_uncore_write(uncore, PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); I915_READ 3384 drivers/gpu/drm/i915/i915_irq.c hotplug = I915_READ(PCH_PORT_HOTPLUG); I915_READ 3423 drivers/gpu/drm/i915/i915_irq.c hotplug = I915_READ(SHOTPLUG_CTL_DDI); I915_READ 3428 drivers/gpu/drm/i915/i915_irq.c hotplug = I915_READ(SHOTPLUG_CTL_TC); I915_READ 3476 drivers/gpu/drm/i915/i915_irq.c hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL); I915_READ 3483 drivers/gpu/drm/i915/i915_irq.c hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL); I915_READ 3501 drivers/gpu/drm/i915/i915_irq.c val = I915_READ(GEN11_DE_HPD_IMR); I915_READ 3520 drivers/gpu/drm/i915/i915_irq.c val = I915_READ(SOUTH_CHICKEN1); I915_READ 3527 drivers/gpu/drm/i915/i915_irq.c hotplug = I915_READ(PCH_PORT_HOTPLUG); I915_READ 3534 drivers/gpu/drm/i915/i915_irq.c hotplug = I915_READ(PCH_PORT_HOTPLUG2); I915_READ 3560 drivers/gpu/drm/i915/i915_irq.c hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); I915_READ 3598 drivers/gpu/drm/i915/i915_irq.c hotplug = I915_READ(PCH_PORT_HOTPLUG); I915_READ 3846 drivers/gpu/drm/i915/i915_irq.c WARN_ON(I915_READ(SDEIER) != 0); I915_READ 3980 drivers/gpu/drm/i915/i915_irq.c *eir = I915_READ(EIR); I915_READ 3984 drivers/gpu/drm/i915/i915_irq.c *eir_stuck = I915_READ(EIR); I915_READ 3998 drivers/gpu/drm/i915/i915_irq.c emr = I915_READ(EMR); I915_READ 4063 drivers/gpu/drm/i915/i915_irq.c I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); I915_READ 4129 drivers/gpu/drm/i915/i915_irq.c iir = I915_READ(GEN2_IIR); I915_READ 4170 drivers/gpu/drm/i915/i915_irq.c I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); I915_READ 4272 drivers/gpu/drm/i915/i915_irq.c iir = I915_READ(GEN2_IIR); I915_READ 422 drivers/gpu/drm/i915/i915_perf.c return I915_READ(GEN8_OATAILPTR) & GEN8_OATAILPTR_MASK; I915_READ 428 drivers/gpu/drm/i915/i915_perf.c u32 oastatus1 = I915_READ(GEN7_OASTATUS1); I915_READ 874 drivers/gpu/drm/i915/i915_perf.c oastatus = I915_READ(GEN8_OASTATUS); I915_READ 906 drivers/gpu/drm/i915/i915_perf.c oastatus = I915_READ(GEN8_OASTATUS); I915_READ 1085 drivers/gpu/drm/i915/i915_perf.c oastatus1 = I915_READ(GEN7_OASTATUS1); I915_READ 1126 drivers/gpu/drm/i915/i915_perf.c oastatus1 = I915_READ(GEN7_OASTATUS1); I915_READ 1619 drivers/gpu/drm/i915/i915_perf.c I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & I915_READ 1621 drivers/gpu/drm/i915/i915_perf.c I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) | I915_READ 1637 drivers/gpu/drm/i915/i915_perf.c I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) & I915_READ 1639 drivers/gpu/drm/i915/i915_perf.c I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) | I915_READ 1642 drivers/gpu/drm/i915/i915_perf.c I915_WRITE(GDT_CHICKEN_BITS, (I915_READ(GDT_CHICKEN_BITS) & I915_READ 2005 drivers/gpu/drm/i915/i915_perf.c I915_WRITE(GDT_CHICKEN_BITS, (I915_READ(GDT_CHICKEN_BITS) & I915_READ 2018 drivers/gpu/drm/i915/i915_perf.c I915_READ(RPM_CONFIG1) & ~GEN10_GT_NOA_ENABLE); I915_READ 40 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); I915_READ 44 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); I915_READ 78 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); I915_READ 81 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); I915_READ 86 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); I915_READ 87 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); I915_READ 90 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i)); I915_READ 93 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); I915_READ 96 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); I915_READ 97 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); I915_READ 100 drivers/gpu/drm/i915/i915_suspend.c dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i)); I915_READ 276 drivers/gpu/drm/i915/i915_sysfs.c freq = intel_get_cagf(dev_priv, I915_READ(GEN6_RPSTAT1)); I915_READ 279 drivers/gpu/drm/i915/intel_csr.c val = I915_READ(DC_STATE_DEBUG); I915_READ 204 drivers/gpu/drm/i915/intel_device_info.c s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; I915_READ 205 drivers/gpu/drm/i915/intel_device_info.c ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE); I915_READ 207 drivers/gpu/drm/i915/intel_device_info.c eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK); I915_READ 234 drivers/gpu/drm/i915/intel_device_info.c const u32 fuse2 = I915_READ(GEN8_FUSE2); I915_READ 258 drivers/gpu/drm/i915/intel_device_info.c eu_en = ~I915_READ(GEN8_EU_DISABLE0); I915_READ 263 drivers/gpu/drm/i915/intel_device_info.c eu_en = ~I915_READ(GEN8_EU_DISABLE1); I915_READ 270 drivers/gpu/drm/i915/intel_device_info.c eu_en = ~I915_READ(GEN8_EU_DISABLE2); I915_READ 277 drivers/gpu/drm/i915/intel_device_info.c eu_en = ~I915_READ(GEN10_EU_DISABLE3); I915_READ 314 drivers/gpu/drm/i915/intel_device_info.c fuse = I915_READ(CHV_FUSE_GT); I915_READ 371 drivers/gpu/drm/i915/intel_device_info.c fuse2 = I915_READ(GEN8_FUSE2); I915_READ 398 drivers/gpu/drm/i915/intel_device_info.c eu_disable = I915_READ(GEN9_EU_DISABLE(s)); I915_READ 474 drivers/gpu/drm/i915/intel_device_info.c fuse2 = I915_READ(GEN8_FUSE2); I915_READ 488 drivers/gpu/drm/i915/intel_device_info.c eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK; I915_READ 489 drivers/gpu/drm/i915/intel_device_info.c eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) | I915_READ 490 drivers/gpu/drm/i915/intel_device_info.c ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) << I915_READ 492 drivers/gpu/drm/i915/intel_device_info.c eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) | I915_READ 493 drivers/gpu/drm/i915/intel_device_info.c ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) << I915_READ 583 drivers/gpu/drm/i915/intel_device_info.c fuse1 = I915_READ(HSW_PAVP_FUSE1); I915_READ 618 drivers/gpu/drm/i915/intel_device_info.c u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE); I915_READ 702 drivers/gpu/drm/i915/intel_device_info.c u32 ctc_reg = I915_READ(CTC_MODE); I915_READ 720 drivers/gpu/drm/i915/intel_device_info.c u32 ctc_reg = I915_READ(CTC_MODE); I915_READ 731 drivers/gpu/drm/i915/intel_device_info.c u32 rpm_config_reg = I915_READ(RPM_CONFIG0); I915_READ 909 drivers/gpu/drm/i915/intel_device_info.c u32 fuse_strap = I915_READ(FUSE_STRAP); I915_READ 910 drivers/gpu/drm/i915/intel_device_info.c u32 sfuse_strap = I915_READ(SFUSE_STRAP); I915_READ 932 drivers/gpu/drm/i915/intel_device_info.c u32 dfsm = I915_READ(SKL_DFSM); I915_READ 1006 drivers/gpu/drm/i915/intel_device_info.c media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE); I915_READ 79 drivers/gpu/drm/i915/intel_pm.c I915_READ(CHICKEN_PAR1_1) | I915_READ 85 drivers/gpu/drm/i915/intel_pm.c I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); I915_READ 89 drivers/gpu/drm/i915/intel_pm.c I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); I915_READ 93 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | I915_READ 98 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | I915_READ 103 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) I915_READ 113 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | I915_READ 120 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | I915_READ 127 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | I915_READ 148 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | I915_READ 153 drivers/gpu/drm/i915/intel_pm.c u32 val = I915_READ(CHICKEN_MISC_2); I915_READ 166 drivers/gpu/drm/i915/intel_pm.c tmp = I915_READ(CLKCFG); I915_READ 196 drivers/gpu/drm/i915/intel_pm.c tmp = I915_READ(CSHRDDR3CTL); I915_READ 376 drivers/gpu/drm/i915/intel_pm.c was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; I915_READ 380 drivers/gpu/drm/i915/intel_pm.c was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; I915_READ 384 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(DSPFW3); I915_READ 393 drivers/gpu/drm/i915/intel_pm.c was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; I915_READ 404 drivers/gpu/drm/i915/intel_pm.c was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; I915_READ 504 drivers/gpu/drm/i915/intel_pm.c dsparb = I915_READ(DSPARB); I915_READ 505 drivers/gpu/drm/i915/intel_pm.c dsparb2 = I915_READ(DSPARB2); I915_READ 510 drivers/gpu/drm/i915/intel_pm.c dsparb = I915_READ(DSPARB); I915_READ 511 drivers/gpu/drm/i915/intel_pm.c dsparb2 = I915_READ(DSPARB2); I915_READ 516 drivers/gpu/drm/i915/intel_pm.c dsparb2 = I915_READ(DSPARB2); I915_READ 517 drivers/gpu/drm/i915/intel_pm.c dsparb3 = I915_READ(DSPARB3); I915_READ 535 drivers/gpu/drm/i915/intel_pm.c u32 dsparb = I915_READ(DSPARB); I915_READ 551 drivers/gpu/drm/i915/intel_pm.c u32 dsparb = I915_READ(DSPARB); I915_READ 568 drivers/gpu/drm/i915/intel_pm.c u32 dsparb = I915_READ(DSPARB); I915_READ 892 drivers/gpu/drm/i915/intel_pm.c reg = I915_READ(DSPFW1); I915_READ 902 drivers/gpu/drm/i915/intel_pm.c reg = I915_READ(DSPFW3); I915_READ 911 drivers/gpu/drm/i915/intel_pm.c reg = I915_READ(DSPFW3); I915_READ 920 drivers/gpu/drm/i915/intel_pm.c reg = I915_READ(DSPFW3); I915_READ 2441 drivers/gpu/drm/i915/intel_pm.c fwater_lo = I915_READ(FW_BLC) & ~0xfff; I915_READ 3578 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(WM_MISC); I915_READ 3585 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(DISP_ARB_CTL2); I915_READ 3595 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(DISP_ARB_CTL); I915_READ 3647 drivers/gpu/drm/i915/intel_pm.c if (0 && I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE) I915_READ 3996 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(CUR_BUF_CFG(pipe)); I915_READ 4001 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(PLANE_CTL(pipe, plane_id)); I915_READ 4010 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(PLANE_BUF_CFG(pipe, plane_id)); I915_READ 4013 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(PLANE_BUF_CFG(pipe, plane_id)); I915_READ 4014 drivers/gpu/drm/i915/intel_pm.c val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id)); I915_READ 5784 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(PLANE_WM(pipe, plane_id, level)); I915_READ 5786 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(CUR_WM(pipe, level)); I915_READ 5792 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(PLANE_WM_TRANS(pipe, plane_id)); I915_READ 5794 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(CUR_WM_TRANS(pipe)); I915_READ 5802 drivers/gpu/drm/i915/intel_pm.c out->linetime = I915_READ(PIPE_WM_LINETIME(pipe)); I915_READ 5842 drivers/gpu/drm/i915/intel_pm.c hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); I915_READ 5844 drivers/gpu/drm/i915/intel_pm.c hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); I915_READ 5889 drivers/gpu/drm/i915/intel_pm.c tmp = I915_READ(DSPFW1); I915_READ 5895 drivers/gpu/drm/i915/intel_pm.c tmp = I915_READ(DSPFW2); I915_READ 5903 drivers/gpu/drm/i915/intel_pm.c tmp = I915_READ(DSPFW3); I915_READ 5917 drivers/gpu/drm/i915/intel_pm.c tmp = I915_READ(VLV_DDL(pipe)); I915_READ 5929 drivers/gpu/drm/i915/intel_pm.c tmp = I915_READ(DSPFW1); I915_READ 5935 drivers/gpu/drm/i915/intel_pm.c tmp = I915_READ(DSPFW2); I915_READ 5940 drivers/gpu/drm/i915/intel_pm.c tmp = I915_READ(DSPFW3); I915_READ 5944 drivers/gpu/drm/i915/intel_pm.c tmp = I915_READ(DSPFW7_CHV); I915_READ 5948 drivers/gpu/drm/i915/intel_pm.c tmp = I915_READ(DSPFW8_CHV); I915_READ 5952 drivers/gpu/drm/i915/intel_pm.c tmp = I915_READ(DSPFW9_CHV); I915_READ 5956 drivers/gpu/drm/i915/intel_pm.c tmp = I915_READ(DSPHOWM); I915_READ 5968 drivers/gpu/drm/i915/intel_pm.c tmp = I915_READ(DSPFW7); I915_READ 5972 drivers/gpu/drm/i915/intel_pm.c tmp = I915_READ(DSPHOWM); I915_READ 5993 drivers/gpu/drm/i915/intel_pm.c wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; I915_READ 6134 drivers/gpu/drm/i915/intel_pm.c wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; I915_READ 6278 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); I915_READ 6279 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); I915_READ 6280 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); I915_READ 6298 drivers/gpu/drm/i915/intel_pm.c hw->wm_lp[0] = I915_READ(WM1_LP_ILK); I915_READ 6299 drivers/gpu/drm/i915/intel_pm.c hw->wm_lp[1] = I915_READ(WM2_LP_ILK); I915_READ 6300 drivers/gpu/drm/i915/intel_pm.c hw->wm_lp[2] = I915_READ(WM3_LP_ILK); I915_READ 6302 drivers/gpu/drm/i915/intel_pm.c hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); I915_READ 6304 drivers/gpu/drm/i915/intel_pm.c hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); I915_READ 6305 drivers/gpu/drm/i915/intel_pm.c hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); I915_READ 6309 drivers/gpu/drm/i915/intel_pm.c hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? I915_READ 6312 drivers/gpu/drm/i915/intel_pm.c hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? I915_READ 6316 drivers/gpu/drm/i915/intel_pm.c !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); I915_READ 6367 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(DISP_ARB_CTL2); I915_READ 6440 drivers/gpu/drm/i915/intel_pm.c intel_uncore_write16(uncore, PMMISC, I915_READ(PMMISC) | MCPPCE_EN); I915_READ 6441 drivers/gpu/drm/i915/intel_pm.c intel_uncore_write16(uncore, TSC1, I915_READ(TSC1) | TSE); I915_READ 6981 drivers/gpu/drm/i915/intel_pm.c rc_ctl = I915_READ(GEN6_RC_CONTROL); I915_READ 6982 drivers/gpu/drm/i915/intel_pm.c rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >> I915_READ 6990 drivers/gpu/drm/i915/intel_pm.c if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) { I915_READ 6999 drivers/gpu/drm/i915/intel_pm.c rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK; I915_READ 7006 drivers/gpu/drm/i915/intel_pm.c if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) && I915_READ 7007 drivers/gpu/drm/i915/intel_pm.c ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) && I915_READ 7008 drivers/gpu/drm/i915/intel_pm.c ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) && I915_READ 7009 drivers/gpu/drm/i915/intel_pm.c ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) { I915_READ 7014 drivers/gpu/drm/i915/intel_pm.c if (!I915_READ(GEN8_PUSHBUS_CONTROL) || I915_READ 7015 drivers/gpu/drm/i915/intel_pm.c !I915_READ(GEN8_PUSHBUS_ENABLE) || I915_READ 7016 drivers/gpu/drm/i915/intel_pm.c !I915_READ(GEN8_PUSHBUS_SHIFT)) { I915_READ 7021 drivers/gpu/drm/i915/intel_pm.c if (!I915_READ(GEN6_GFXPAUSE)) { I915_READ 7026 drivers/gpu/drm/i915/intel_pm.c if (!I915_READ(GEN8_MISC_CTRL0)) { I915_READ 7070 drivers/gpu/drm/i915/intel_pm.c u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP); I915_READ 7075 drivers/gpu/drm/i915/intel_pm.c u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); I915_READ 7396 drivers/gpu/drm/i915/intel_pm.c gtfifodbg = I915_READ(GTFIFODBG); I915_READ 7503 drivers/gpu/drm/i915/intel_pm.c min_ring_freq = I915_READ(DCLK) & 0xf; I915_READ 7673 drivers/gpu/drm/i915/intel_pm.c unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; I915_READ 7683 drivers/gpu/drm/i915/intel_pm.c unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; I915_READ 7694 drivers/gpu/drm/i915/intel_pm.c pcbr = I915_READ(VLV_PCBR); I915_READ 7704 drivers/gpu/drm/i915/intel_pm.c DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); I915_READ 7714 drivers/gpu/drm/i915/intel_pm.c pcbr = I915_READ(VLV_PCBR); I915_READ 7751 drivers/gpu/drm/i915/intel_pm.c DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); I915_READ 7899 drivers/gpu/drm/i915/intel_pm.c gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV | I915_READ 7935 drivers/gpu/drm/i915/intel_pm.c pcbr = I915_READ(VLV_PCBR); I915_READ 7998 drivers/gpu/drm/i915/intel_pm.c gtfifodbg = I915_READ(GTFIFODBG); I915_READ 8124 drivers/gpu/drm/i915/intel_pm.c count1 = I915_READ(DMIEC); I915_READ 8125 drivers/gpu/drm/i915/intel_pm.c count2 = I915_READ(DDREC); I915_READ 8126 drivers/gpu/drm/i915/intel_pm.c count3 = I915_READ(CSIEC); I915_READ 8228 drivers/gpu/drm/i915/intel_pm.c count = I915_READ(GFXEC); I915_READ 8267 drivers/gpu/drm/i915/intel_pm.c pxvid = I915_READ(PXVFREQ(dev_priv->gt_pm.rps.cur_freq)); I915_READ 8508 drivers/gpu/drm/i915/intel_pm.c u32 pxvidfreq = I915_READ(PXVFREQ(i)); I915_READ 8550 drivers/gpu/drm/i915/intel_pm.c lcfuse = I915_READ(LCFUSE02); I915_READ 8557 drivers/gpu/drm/i915/intel_pm.c return !I915_READ(GEN8_RC6_CTX_INFO); I915_READ 8898 drivers/gpu/drm/i915/intel_pm.c I915_READ(DSPCNTR(pipe)) | I915_READ 8901 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); I915_READ 8932 drivers/gpu/drm/i915/intel_pm.c (I915_READ(ILK_DISPLAY_CHICKEN2) | I915_READ 8936 drivers/gpu/drm/i915/intel_pm.c (I915_READ(DISP_ARB_CTL) | I915_READ 8949 drivers/gpu/drm/i915/intel_pm.c I915_READ(ILK_DISPLAY_CHICKEN1) | I915_READ 8952 drivers/gpu/drm/i915/intel_pm.c I915_READ(ILK_DISPLAY_CHICKEN2) | I915_READ 8959 drivers/gpu/drm/i915/intel_pm.c I915_READ(ILK_DISPLAY_CHICKEN2) | I915_READ 8990 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | I915_READ 8996 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(TRANS_CHICKEN2(pipe)); I915_READ 9017 drivers/gpu/drm/i915/intel_pm.c tmp = I915_READ(MCH_SSKPD); I915_READ 9030 drivers/gpu/drm/i915/intel_pm.c I915_READ(ILK_DISPLAY_CHICKEN2) | I915_READ 9055 drivers/gpu/drm/i915/intel_pm.c I915_READ(GEN6_UCGCTL1) | I915_READ 9100 drivers/gpu/drm/i915/intel_pm.c I915_READ(ILK_DISPLAY_CHICKEN1) | I915_READ 9103 drivers/gpu/drm/i915/intel_pm.c I915_READ(ILK_DISPLAY_CHICKEN2) | I915_READ 9106 drivers/gpu/drm/i915/intel_pm.c I915_READ(ILK_DSPCLK_GATE_D) | I915_READ 9119 drivers/gpu/drm/i915/intel_pm.c u32 reg = I915_READ(GEN7_FF_THREAD_MODE); I915_READ 9143 drivers/gpu/drm/i915/intel_pm.c I915_READ(SOUTH_DSPCLK_GATE_D) | I915_READ 9148 drivers/gpu/drm/i915/intel_pm.c I915_READ(TRANS_CHICKEN1(PIPE_A)) | I915_READ 9155 drivers/gpu/drm/i915/intel_pm.c u32 val = I915_READ(SOUTH_DSPCLK_GATE_D); I915_READ 9170 drivers/gpu/drm/i915/intel_pm.c misccpctl = I915_READ(GEN7_MISCCPCTL); I915_READ 9173 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(GEN8_L3SQCREG1); I915_READ 9192 drivers/gpu/drm/i915/intel_pm.c I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE); I915_READ 9216 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) | I915_READ 9231 drivers/gpu/drm/i915/intel_pm.c I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); I915_READ 9234 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | I915_READ 9237 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(SLICE_UNIT_LEVEL_CLKGATE); I915_READ 9246 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE); I915_READ 9252 drivers/gpu/drm/i915/intel_pm.c val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE); I915_READ 9263 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | I915_READ 9273 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | I915_READ 9278 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | I915_READ 9282 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | I915_READ 9291 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) | I915_READ 9295 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | I915_READ 9304 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); I915_READ 9308 drivers/gpu/drm/i915/intel_pm.c I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); I915_READ 9313 drivers/gpu/drm/i915/intel_pm.c I915_READ(CHICKEN_PIPESL_1(pipe)) | I915_READ 9320 drivers/gpu/drm/i915/intel_pm.c I915_READ(GEN7_FF_THREAD_MODE) & I915_READ 9327 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | I915_READ 9334 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1) I915_READ 9345 drivers/gpu/drm/i915/intel_pm.c I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); I915_READ 9357 drivers/gpu/drm/i915/intel_pm.c I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | I915_READ 9362 drivers/gpu/drm/i915/intel_pm.c I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); I915_READ 9391 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); I915_READ 9440 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & I915_READ 9452 drivers/gpu/drm/i915/intel_pm.c I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | I915_READ 9480 drivers/gpu/drm/i915/intel_pm.c snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); I915_READ 9512 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & I915_READ 9521 drivers/gpu/drm/i915/intel_pm.c I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | I915_READ 9537 drivers/gpu/drm/i915/intel_pm.c I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); I915_READ 9576 drivers/gpu/drm/i915/intel_pm.c I915_READ(GEN7_FF_THREAD_MODE) & I915_READ 9584 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | I915_READ 9588 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | I915_READ 9661 drivers/gpu/drm/i915/intel_pm.c u32 dstate = I915_READ(D_STATE); I915_READ 301 drivers/gpu/drm/i915/selftests/intel_uncore.c (void)I915_READ(reg);