I915_NUM_ENGINES  289 drivers/gpu/drm/i915/gem/i915_gem_context.c 	e = kzalloc(struct_size(e, engines, I915_NUM_ENGINES), GFP_KERNEL);
I915_NUM_ENGINES  992 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 	static struct intel_engine_cs *engines[I915_NUM_ENGINES];
I915_NUM_ENGINES 1032 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 	order = i915_random_order(n * I915_NUM_ENGINES, &prng);
I915_NUM_ENGINES 1048 drivers/gpu/drm/i915/gem/selftests/huge_pages.c 		i = (i + 1) % (n * I915_NUM_ENGINES);
I915_NUM_ENGINES  293 drivers/gpu/drm/i915/gt/intel_engine_cs.c 	BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
I915_NUM_ENGINES  408 drivers/gpu/drm/i915/gt/intel_engine_cs.c 		GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
I915_NUM_ENGINES   82 drivers/gpu/drm/i915/gt/intel_gt_types.h 	struct intel_engine_cs *engine[I915_NUM_ENGINES];
I915_NUM_ENGINES  204 drivers/gpu/drm/i915/gt/intel_lrc.c 	} nodes[I915_NUM_ENGINES];
I915_NUM_ENGINES  242 drivers/gpu/drm/i915/gt/mock_engine.c 	GEM_BUG_ON(id >= I915_NUM_ENGINES);
I915_NUM_ENGINES  809 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 		struct active_engine threads[I915_NUM_ENGINES] = {};
I915_NUM_ENGINES 1510 drivers/gpu/drm/i915/gt/selftest_lrc.c 	struct task_struct *tsk[I915_NUM_ENGINES] = {};
I915_NUM_ENGINES 1511 drivers/gpu/drm/i915/gt/selftest_lrc.c 	struct preempt_smoke arg[I915_NUM_ENGINES];
I915_NUM_ENGINES  246 drivers/gpu/drm/i915/gt/selftest_timeline.c 	return i915_prandom_u32_max_state(I915_NUM_ENGINES, rnd);
I915_NUM_ENGINES  512 drivers/gpu/drm/i915/gt/selftest_timeline.c 	timelines = kvmalloc_array(NUM_TIMELINES * I915_NUM_ENGINES,
I915_NUM_ENGINES  588 drivers/gpu/drm/i915/gt/selftest_timeline.c 	timelines = kvmalloc_array(NUM_TIMELINES * I915_NUM_ENGINES,
I915_NUM_ENGINES   33 drivers/gpu/drm/i915/gt/selftest_workarounds.c 	} engine[I915_NUM_ENGINES];
I915_NUM_ENGINES 1137 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 		     I915_NUM_ENGINES > GUC_WQ_SIZE);
I915_NUM_ENGINES  579 drivers/gpu/drm/i915/gvt/cmd_parser.c static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
I915_NUM_ENGINES 3036 drivers/gpu/drm/i915/gvt/cmd_parser.c 	for_each_set_bit(ring, &rings, I915_NUM_ENGINES) {
I915_NUM_ENGINES  150 drivers/gpu/drm/i915/gvt/debugfs.c 	val &= (1 << I915_NUM_ENGINES) - 1;
I915_NUM_ENGINES  164 drivers/gpu/drm/i915/gvt/debugfs.c 	for (id = 0; id < I915_NUM_ENGINES; id++) {
I915_NUM_ENGINES  150 drivers/gpu/drm/i915/gvt/gvt.h 	struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
I915_NUM_ENGINES  151 drivers/gpu/drm/i915/gvt/gvt.h 	struct list_head workload_q_head[I915_NUM_ENGINES];
I915_NUM_ENGINES  152 drivers/gpu/drm/i915/gvt/gvt.h 	struct intel_context *shadow[I915_NUM_ENGINES];
I915_NUM_ENGINES  159 drivers/gpu/drm/i915/gvt/gvt.h 	DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
I915_NUM_ENGINES  160 drivers/gpu/drm/i915/gvt/gvt.h 	DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
I915_NUM_ENGINES  161 drivers/gpu/drm/i915/gvt/gvt.h 	void *ring_scan_buffer[I915_NUM_ENGINES];
I915_NUM_ENGINES  162 drivers/gpu/drm/i915/gvt/gvt.h 	int ring_scan_buffer_size[I915_NUM_ENGINES];
I915_NUM_ENGINES  195 drivers/gpu/drm/i915/gvt/gvt.h 	u32 hws_pga[I915_NUM_ENGINES];
I915_NUM_ENGINES  320 drivers/gpu/drm/i915/gvt/gvt.h 	struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES];
I915_NUM_ENGINES  336 drivers/gpu/drm/i915/gvt/gvt.h 		int ctx_mmio_count[I915_NUM_ENGINES];
I915_NUM_ENGINES 1485 drivers/gpu/drm/i915/gvt/handlers.c 	if (unlikely(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) {
I915_NUM_ENGINES 1672 drivers/gpu/drm/i915/gvt/handlers.c 	if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES))
I915_NUM_ENGINES  147 drivers/gpu/drm/i915/gvt/mmio_context.c 	u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE];
I915_NUM_ENGINES  470 drivers/gpu/drm/i915/gvt/sched_policy.c 	for (ring_id = 0; ring_id < I915_NUM_ENGINES; ring_id++) {
I915_NUM_ENGINES 1281 drivers/gpu/drm/i915/gvt/scheduler.c 	bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
I915_NUM_ENGINES 1296 drivers/gpu/drm/i915/gvt/scheduler.c 	bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES);
I915_NUM_ENGINES   42 drivers/gpu/drm/i915/gvt/scheduler.h 	struct intel_vgpu_workload *current_workload[I915_NUM_ENGINES];
I915_NUM_ENGINES   47 drivers/gpu/drm/i915/gvt/scheduler.h 	struct intel_vgpu *engine_owner[I915_NUM_ENGINES];
I915_NUM_ENGINES   50 drivers/gpu/drm/i915/gvt/scheduler.h 	struct task_struct *thread[I915_NUM_ENGINES];
I915_NUM_ENGINES   51 drivers/gpu/drm/i915/gvt/scheduler.h 	wait_queue_head_t waitq[I915_NUM_ENGINES];
I915_NUM_ENGINES  333 drivers/gpu/drm/i915/gvt/vgpu.c 	for (i = 0; i < I915_NUM_ENGINES; i++)
I915_NUM_ENGINES 1350 drivers/gpu/drm/i915/i915_drv.h 	struct intel_engine_cs *engine[I915_NUM_ENGINES];
I915_NUM_ENGINES 1794 drivers/gpu/drm/i915/i915_drv.h 	     (id__) < I915_NUM_ENGINES; \
I915_NUM_ENGINES 1259 drivers/gpu/drm/i915/i915_gem.c 	struct i915_request *requests[I915_NUM_ENGINES] = {};
I915_NUM_ENGINES  181 drivers/gpu/drm/i915/i915_gpu_error.h 	atomic_t reset_engine_count[I915_NUM_ENGINES];
I915_NUM_ENGINES  874 drivers/gpu/drm/i915/intel_device_info.c 	BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
I915_NUM_ENGINES  836 drivers/gpu/drm/i915/selftests/i915_request.c 	struct i915_request *request[I915_NUM_ENGINES];
I915_NUM_ENGINES  938 drivers/gpu/drm/i915/selftests/i915_request.c 	struct i915_request *request[I915_NUM_ENGINES] = {};
I915_NUM_ENGINES 1105 drivers/gpu/drm/i915/selftests/i915_request.c 	struct smoketest t[I915_NUM_ENGINES];
I915_NUM_ENGINES 1133 drivers/gpu/drm/i915/selftests/i915_request.c 	threads = kcalloc(ncpus * I915_NUM_ENGINES,
I915_NUM_ENGINES   20 drivers/gpu/drm/i915/selftests/igt_live_test.h 	unsigned int reset_engine[I915_NUM_ENGINES];