I8259A_IRQ_BASE    89 arch/mips/include/asm/i8259.h 	return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
I8259A_IRQ_BASE    50 arch/mips/include/asm/irq.h 	return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq);
I8259A_IRQ_BASE    26 arch/mips/include/asm/mach-cobalt/irq.h #define PCISLOT_IRQ			(I8259A_IRQ_BASE + 9)
I8259A_IRQ_BASE    16 arch/mips/include/asm/mach-generic/irq.h #ifndef I8259A_IRQ_BASE
I8259A_IRQ_BASE    18 arch/mips/include/asm/txx9irq.h #define TXX9_IRQ_BASE	(I8259A_IRQ_BASE + 16)
I8259A_IRQ_BASE   139 arch/mips/loongson64/loongson-3/irq.c 	chip = irq_get_chip(I8259A_IRQ_BASE);
I8259A_IRQ_BASE   185 arch/mips/mti-malta/malta-int.c 	WARN(irq_alloc_descs(I8259A_IRQ_BASE, I8259A_IRQ_BASE,
I8259A_IRQ_BASE   187 arch/mips/mti-malta/malta-int.c 		"Cannot reserve i8259 virqs at IRQ%d\n", I8259A_IRQ_BASE);
I8259A_IRQ_BASE   248 arch/mips/txx9/generic/pci.c 	if (unlikely(isairq <= I8259A_IRQ_BASE))
I8259A_IRQ_BASE    70 drivers/irqchip/irq-i8259.c 	unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
I8259A_IRQ_BASE    85 drivers/irqchip/irq-i8259.c 	unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
I8259A_IRQ_BASE   136 drivers/irqchip/irq-i8259.c 	unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE;
I8259A_IRQ_BASE   243 drivers/irqchip/irq-i8259.c 	outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR);	/* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */
I8259A_IRQ_BASE   251 drivers/irqchip/irq-i8259.c 	outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR);	/* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */
I8259A_IRQ_BASE   321 drivers/irqchip/irq-i8259.c 	domain = irq_domain_add_legacy(node, 16, I8259A_IRQ_BASE, 0,
I8259A_IRQ_BASE   326 drivers/irqchip/irq-i8259.c 	setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);