Hit_Writeback_Inv_D   82 arch/mips/include/asm/r4kcache.h 	cache_op(Hit_Writeback_Inv_D, addr);
Hit_Writeback_Inv_D  173 arch/mips/include/asm/r4kcache.h 	return protected_cachee_op(Hit_Writeback_Inv_D, addr);
Hit_Writeback_Inv_D  175 arch/mips/include/asm/r4kcache.h 	return protected_cache_op(Hit_Writeback_Inv_D, addr);
Hit_Writeback_Inv_D  571 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
Hit_Writeback_Inv_D  574 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
Hit_Writeback_Inv_D  578 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
Hit_Writeback_Inv_D  581 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
Hit_Writeback_Inv_D  604 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
Hit_Writeback_Inv_D  607 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
Hit_Writeback_Inv_D  610 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
Hit_Writeback_Inv_D  633 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
Hit_Writeback_Inv_D  664 arch/mips/include/asm/r4kcache.h __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
Hit_Writeback_Inv_D  671 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
Hit_Writeback_Inv_D 1883 arch/mips/kvm/emulate.c 	if (op_inst == Hit_Writeback_Inv_D || op_inst == Hit_Invalidate_D) {
Hit_Writeback_Inv_D 1110 arch/mips/kvm/vz.c 	case Hit_Writeback_Inv_D: