HYDRA_TS_CTRL_BASE_ADDR  167 drivers/media/dvb-frontends/mxl5xx_regs.h #define MPEG_MUX_MODE_SLICE0_REG            (HYDRA_TS_CTRL_BASE_ADDR + 0x08)
HYDRA_TS_CTRL_BASE_ADDR  169 drivers/media/dvb-frontends/mxl5xx_regs.h #define MPEG_MUX_MODE_SLICE1_REG            (HYDRA_TS_CTRL_BASE_ADDR + 0x08)
HYDRA_TS_CTRL_BASE_ADDR  171 drivers/media/dvb-frontends/mxl5xx_regs.h #define PID_BANK_SEL_SLICE0_REG             (HYDRA_TS_CTRL_BASE_ADDR + 0x190)
HYDRA_TS_CTRL_BASE_ADDR  172 drivers/media/dvb-frontends/mxl5xx_regs.h #define PID_BANK_SEL_SLICE1_REG             (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0)
HYDRA_TS_CTRL_BASE_ADDR  174 drivers/media/dvb-frontends/mxl5xx_regs.h #define MPEG_CLK_GATED_REG                  (HYDRA_TS_CTRL_BASE_ADDR + 0x20)
HYDRA_TS_CTRL_BASE_ADDR  176 drivers/media/dvb-frontends/mxl5xx_regs.h #define MPEG_CLK_ALWAYS_ON_REG              (HYDRA_TS_CTRL_BASE_ADDR + 0x1D4)
HYDRA_TS_CTRL_BASE_ADDR  178 drivers/media/dvb-frontends/mxl5xx_regs.h #define HYDRA_REGULAR_PID_BANK_A_REG        (HYDRA_TS_CTRL_BASE_ADDR + 0x190)
HYDRA_TS_CTRL_BASE_ADDR  180 drivers/media/dvb-frontends/mxl5xx_regs.h #define HYDRA_FIXED_PID_BANK_A_REG          (HYDRA_TS_CTRL_BASE_ADDR + 0x190)
HYDRA_TS_CTRL_BASE_ADDR  182 drivers/media/dvb-frontends/mxl5xx_regs.h #define HYDRA_REGULAR_PID_BANK_B_REG        (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0)
HYDRA_TS_CTRL_BASE_ADDR  184 drivers/media/dvb-frontends/mxl5xx_regs.h #define HYDRA_FIXED_PID_BANK_B_REG          (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0)
HYDRA_TS_CTRL_BASE_ADDR  186 drivers/media/dvb-frontends/mxl5xx_regs.h #define FIXED_PID_TBL_REG_ADDRESS_0         (HYDRA_TS_CTRL_BASE_ADDR + 0x9000)
HYDRA_TS_CTRL_BASE_ADDR  187 drivers/media/dvb-frontends/mxl5xx_regs.h #define FIXED_PID_TBL_REG_ADDRESS_1         (HYDRA_TS_CTRL_BASE_ADDR + 0x9100)
HYDRA_TS_CTRL_BASE_ADDR  188 drivers/media/dvb-frontends/mxl5xx_regs.h #define FIXED_PID_TBL_REG_ADDRESS_2         (HYDRA_TS_CTRL_BASE_ADDR + 0x9200)
HYDRA_TS_CTRL_BASE_ADDR  189 drivers/media/dvb-frontends/mxl5xx_regs.h #define FIXED_PID_TBL_REG_ADDRESS_3         (HYDRA_TS_CTRL_BASE_ADDR + 0x9300)
HYDRA_TS_CTRL_BASE_ADDR  191 drivers/media/dvb-frontends/mxl5xx_regs.h #define FIXED_PID_TBL_REG_ADDRESS_4         (HYDRA_TS_CTRL_BASE_ADDR + 0xB000)
HYDRA_TS_CTRL_BASE_ADDR  192 drivers/media/dvb-frontends/mxl5xx_regs.h #define FIXED_PID_TBL_REG_ADDRESS_5         (HYDRA_TS_CTRL_BASE_ADDR + 0xB100)
HYDRA_TS_CTRL_BASE_ADDR  193 drivers/media/dvb-frontends/mxl5xx_regs.h #define FIXED_PID_TBL_REG_ADDRESS_6         (HYDRA_TS_CTRL_BASE_ADDR + 0xB200)
HYDRA_TS_CTRL_BASE_ADDR  194 drivers/media/dvb-frontends/mxl5xx_regs.h #define FIXED_PID_TBL_REG_ADDRESS_7         (HYDRA_TS_CTRL_BASE_ADDR + 0xB300)
HYDRA_TS_CTRL_BASE_ADDR  196 drivers/media/dvb-frontends/mxl5xx_regs.h #define REGULAR_PID_TBL_REG_ADDRESS_0       (HYDRA_TS_CTRL_BASE_ADDR + 0x8000)
HYDRA_TS_CTRL_BASE_ADDR  197 drivers/media/dvb-frontends/mxl5xx_regs.h #define REGULAR_PID_TBL_REG_ADDRESS_1       (HYDRA_TS_CTRL_BASE_ADDR + 0x8200)
HYDRA_TS_CTRL_BASE_ADDR  198 drivers/media/dvb-frontends/mxl5xx_regs.h #define REGULAR_PID_TBL_REG_ADDRESS_2       (HYDRA_TS_CTRL_BASE_ADDR + 0x8400)
HYDRA_TS_CTRL_BASE_ADDR  199 drivers/media/dvb-frontends/mxl5xx_regs.h #define REGULAR_PID_TBL_REG_ADDRESS_3       (HYDRA_TS_CTRL_BASE_ADDR + 0x8600)
HYDRA_TS_CTRL_BASE_ADDR  201 drivers/media/dvb-frontends/mxl5xx_regs.h #define REGULAR_PID_TBL_REG_ADDRESS_4       (HYDRA_TS_CTRL_BASE_ADDR + 0xA000)
HYDRA_TS_CTRL_BASE_ADDR  202 drivers/media/dvb-frontends/mxl5xx_regs.h #define REGULAR_PID_TBL_REG_ADDRESS_5       (HYDRA_TS_CTRL_BASE_ADDR + 0xA200)
HYDRA_TS_CTRL_BASE_ADDR  203 drivers/media/dvb-frontends/mxl5xx_regs.h #define REGULAR_PID_TBL_REG_ADDRESS_6       (HYDRA_TS_CTRL_BASE_ADDR + 0xA400)
HYDRA_TS_CTRL_BASE_ADDR  204 drivers/media/dvb-frontends/mxl5xx_regs.h #define REGULAR_PID_TBL_REG_ADDRESS_7       (HYDRA_TS_CTRL_BASE_ADDR + 0xA600)