HW_EVENT_IRQ_BASE   52 arch/sh/boards/mach-dreamcast/irq.c #define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32)
HW_EVENT_IRQ_BASE   55 arch/sh/boards/mach-dreamcast/irq.c #define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31)
HW_EVENT_IRQ_BASE  133 arch/sh/boards/mach-dreamcast/irq.c 			irq = HW_EVENT_IRQ_BASE + j + (level << 5);
HW_EVENT_IRQ_BASE  146 arch/sh/boards/mach-dreamcast/irq.c 	irq_base = irq_alloc_descs(HW_EVENT_IRQ_BASE, HW_EVENT_IRQ_BASE,
HW_EVENT_IRQ_BASE  147 arch/sh/boards/mach-dreamcast/irq.c 				   HW_EVENT_IRQ_MAX - HW_EVENT_IRQ_BASE, -1);
HW_EVENT_IRQ_BASE  153 arch/sh/boards/mach-dreamcast/irq.c 	for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++)
HW_EVENT_IRQ_BASE   28 arch/sh/include/mach-dreamcast/mach/sysasic.h #define HW_EVENT_VSYNC     (HW_EVENT_IRQ_BASE +  5) /* VSync */
HW_EVENT_IRQ_BASE   29 arch/sh/include/mach-dreamcast/mach/sysasic.h #define HW_EVENT_MAPLE_DMA (HW_EVENT_IRQ_BASE + 12) /* Maple DMA complete */
HW_EVENT_IRQ_BASE   30 arch/sh/include/mach-dreamcast/mach/sysasic.h #define HW_EVENT_GDROM_DMA (HW_EVENT_IRQ_BASE + 14) /* GD-ROM DMA complete */
HW_EVENT_IRQ_BASE   31 arch/sh/include/mach-dreamcast/mach/sysasic.h #define HW_EVENT_G2_DMA    (HW_EVENT_IRQ_BASE + 15) /* G2 DMA complete */
HW_EVENT_IRQ_BASE   32 arch/sh/include/mach-dreamcast/mach/sysasic.h #define HW_EVENT_PVR2_DMA  (HW_EVENT_IRQ_BASE + 19) /* PVR2 DMA complete */
HW_EVENT_IRQ_BASE   35 arch/sh/include/mach-dreamcast/mach/sysasic.h #define HW_EVENT_GDROM_CMD (HW_EVENT_IRQ_BASE + 32) /* GD-ROM cmd. complete */
HW_EVENT_IRQ_BASE   36 arch/sh/include/mach-dreamcast/mach/sysasic.h #define HW_EVENT_AICA_SYS  (HW_EVENT_IRQ_BASE + 33) /* AICA-related */
HW_EVENT_IRQ_BASE   37 arch/sh/include/mach-dreamcast/mach/sysasic.h #define HW_EVENT_EXTERNAL  (HW_EVENT_IRQ_BASE + 35) /* Ext. (expansion) */
HW_EVENT_IRQ_BASE   39 arch/sh/include/mach-dreamcast/mach/sysasic.h #define HW_EVENT_IRQ_MAX (HW_EVENT_IRQ_BASE + 95)