HWBLK_URAM 142 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_URAM] = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), HWBLK_URAM 191 arch/sh/kernel/cpu/sh4a/clock-sh7722.c CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]),