HWBLK_SPU         249 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_SPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B],	    MSTPCR2, 9, 0),
HWBLK_SPU         332 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	CLKDEV_DEV_ID("sh_fsi.0", &mstp_clks[HWBLK_SPU]),