HWBLK_DMAC1       157 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	[HWBLK_DMAC1]  = SH_CLK_MSTP32(&div4_clks[DIV4_B],  MSTPCR0, 12, 0),
HWBLK_DMAC1       229 arch/sh/kernel/cpu/sh4a/clock-sh7723.c 	CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[HWBLK_DMAC1]),
HWBLK_DMAC1       218 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	[HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   MSTPCR0, 12, 0),
HWBLK_DMAC1       300 arch/sh/kernel/cpu/sh4a/clock-sh7724.c 	CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[HWBLK_DMAC1]),