HVS_READ          110 drivers/gpu/drm/vc4/vc4_crtc.c 	val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
HVS_READ          418 drivers/gpu/drm/vc4/vc4_crtc.c 		dispctrl = HVS_READ(SCALER_DISPCTRL) &
HVS_READ          448 drivers/gpu/drm/vc4/vc4_crtc.c 	WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
HVS_READ          470 drivers/gpu/drm/vc4/vc4_crtc.c 	if (HVS_READ(SCALER_DISPCTRLX(chan)) &
HVS_READ          483 drivers/gpu/drm/vc4/vc4_crtc.c 	WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
HVS_READ          485 drivers/gpu/drm/vc4/vc4_crtc.c 	WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
HVS_READ          489 drivers/gpu/drm/vc4/vc4_crtc.c 	WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
HVS_READ          730 drivers/gpu/drm/vc4/vc4_crtc.c 			  HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) |
HVS_READ          744 drivers/gpu/drm/vc4/vc4_crtc.c 		u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel));
HVS_READ          792 drivers/gpu/drm/vc4/vc4_crtc.c 	    (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) ||
HVS_READ         1113 drivers/gpu/drm/vc4/vc4_crtc.c 	u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
HVS_READ          160 drivers/gpu/drm/vc4/vc4_hvs.c 	u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
HVS_READ          170 drivers/gpu/drm/vc4/vc4_hvs.c 	u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
HVS_READ          196 drivers/gpu/drm/vc4/vc4_hvs.c 	status = HVS_READ(SCALER_DISPSTAT);
HVS_READ          197 drivers/gpu/drm/vc4/vc4_hvs.c 	control = HVS_READ(SCALER_DISPCTRL);
HVS_READ          272 drivers/gpu/drm/vc4/vc4_hvs.c 	dispctrl = HVS_READ(SCALER_DISPCTRL);