HUBP_SF 244 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\ HUBP_SF 245 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\ HUBP_SF 246 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\ HUBP_SF 247 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\ HUBP_SF 248 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\ HUBP_SF 249 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\ HUBP_SF 250 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\ HUBP_SF 251 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\ HUBP_SF 252 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\ HUBP_SF 253 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\ HUBP_SF 254 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\ HUBP_SF 255 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\ HUBP_SF 256 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\ HUBP_SF 257 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\ HUBP_SF 258 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\ HUBP_SF 259 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\ HUBP_SF 260 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\ HUBP_SF 261 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\ HUBP_SF 262 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\ HUBP_SF 263 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\ HUBP_SF 264 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\ HUBP_SF 265 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\ HUBP_SF 266 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, mask_sh),\ HUBP_SF 267 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, mask_sh),\ HUBP_SF 268 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\ HUBP_SF 269 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\ HUBP_SF 270 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\ HUBP_SF 271 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\ HUBP_SF 272 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\ HUBP_SF 273 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\ HUBP_SF 274 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\ HUBP_SF 275 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\ HUBP_SF 276 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\ HUBP_SF 277 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\ HUBP_SF 278 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\ HUBP_SF 279 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\ HUBP_SF 280 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\ HUBP_SF 281 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\ HUBP_SF 282 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\ HUBP_SF 283 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\ HUBP_SF 284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\ HUBP_SF 285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\ HUBP_SF 286 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ HUBP_SF 287 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\ HUBP_SF 288 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ HUBP_SF 289 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\ HUBP_SF 290 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\ HUBP_SF 291 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\ HUBP_SF 292 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\ HUBP_SF 293 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\ HUBP_SF 294 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\ HUBP_SF 295 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\ HUBP_SF 296 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\ HUBP_SF 297 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\ HUBP_SF 298 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\ HUBP_SF 299 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\ HUBP_SF 300 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\ HUBP_SF 301 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\ HUBP_SF 302 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\ HUBP_SF 303 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ_C, mask_sh),\ HUBP_SF 304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ, mask_sh),\ HUBP_SF 305 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, mask_sh),\ HUBP_SF 306 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\ HUBP_SF 307 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\ HUBP_SF 308 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\ HUBP_SF 309 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\ HUBP_SF 310 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ, mask_sh),\ HUBP_SF 311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\ HUBP_SF 312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\ HUBP_SF 313 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\ HUBP_SF 314 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\ HUBP_SF 315 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\ HUBP_SF 316 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\ HUBP_SF 317 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\ HUBP_SF 318 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\ HUBP_SF 319 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\ HUBP_SF 320 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\ HUBP_SF 321 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\ HUBP_SF 322 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\ HUBP_SF 323 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\ HUBP_SF 324 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\ HUBP_SF 325 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\ HUBP_SF 326 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\ HUBP_SF 327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\ HUBP_SF 328 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\ HUBP_SF 329 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\ HUBP_SF 330 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\ HUBP_SF 331 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\ HUBP_SF 332 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\ HUBP_SF 333 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\ HUBP_SF 334 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\ HUBP_SF 335 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\ HUBP_SF 336 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\ HUBP_SF 337 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\ HUBP_SF 338 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\ HUBP_SF 339 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\ HUBP_SF 340 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\ HUBP_SF 341 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\ HUBP_SF 342 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\ HUBP_SF 343 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\ HUBP_SF 344 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\ HUBP_SF 345 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\ HUBP_SF 346 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\ HUBP_SF 347 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\ HUBP_SF 348 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\ HUBP_SF 349 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\ HUBP_SF 350 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\ HUBP_SF 351 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\ HUBP_SF 352 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\ HUBP_SF 353 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\ HUBP_SF 354 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\ HUBP_SF 355 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\ HUBP_SF 356 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\ HUBP_SF 357 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\ HUBP_SF 358 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\ HUBP_SF 359 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\ HUBP_SF 360 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\ HUBP_SF 361 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ HUBP_SF 362 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ HUBP_SF 363 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\ HUBP_SF 364 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh) HUBP_SF 368 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ HUBP_SF 369 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ HUBP_SF 370 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh) HUBP_SF 378 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\ HUBP_SF 379 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\ HUBP_SF 380 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\ HUBP_SF 381 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\ HUBP_SF 382 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\ HUBP_SF 383 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\ HUBP_SF 384 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\ HUBP_SF 385 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ HUBP_SF 386 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ HUBP_SF 387 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh) HUBP_SF 392 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ HUBP_SF 393 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ HUBP_SF 394 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\ HUBP_SF 395 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\ HUBP_SF 396 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\ HUBP_SF 397 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\ HUBP_SF 398 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\ HUBP_SF 399 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\ HUBP_SF 400 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\ HUBP_SF 401 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\ HUBP_SF 402 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\ HUBP_SF 403 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\ HUBP_SF 404 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, mask_sh),\ HUBP_SF 405 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\ HUBP_SF 406 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\ HUBP_SF 407 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\ HUBP_SF 408 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\ HUBP_SF 409 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\ HUBP_SF 410 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ HUBP_SF 411 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ HUBP_SF 412 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\ HUBP_SF 413 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \ HUBP_SF 414 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ HUBP_SF 415 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ HUBP_SF 416 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ HUBP_SF 417 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ HUBP_SF 418 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ HUBP_SF 419 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ HUBP_SF 420 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ HUBP_SF 421 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ HUBP_SF 422 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ HUBP_SF 423 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ HUBP_SF 424 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ HUBP_SF 425 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ HUBP_SF 426 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ HUBP_SF 427 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ HUBP_SF 428 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh) HUBP_SF 72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ HUBP_SF 73 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ HUBP_SF 74 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\ HUBP_SF 75 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\ HUBP_SF 76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\ HUBP_SF 77 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\ HUBP_SF 78 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\ HUBP_SF 79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \ HUBP_SF 80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ HUBP_SF 81 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ HUBP_SF 82 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ HUBP_SF 83 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ HUBP_SF 84 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ HUBP_SF 85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ HUBP_SF 86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ HUBP_SF 87 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ HUBP_SF 88 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ HUBP_SF 89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ HUBP_SF 90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ HUBP_SF 91 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ HUBP_SF 92 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ HUBP_SF 93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ HUBP_SF 94 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \ HUBP_SF 95 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \ HUBP_SF 96 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \ HUBP_SF 97 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \ HUBP_SF 98 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \ HUBP_SF 99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \ HUBP_SF 100 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \ HUBP_SF 101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \ HUBP_SF 102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \ HUBP_SF 103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \ HUBP_SF 104 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \ HUBP_SF 105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \ HUBP_SF 106 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\ HUBP_SF 107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\ HUBP_SF 108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\ HUBP_SF 109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\ HUBP_SF 110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\ HUBP_SF 111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\ HUBP_SF 112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\ HUBP_SF 113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\ HUBP_SF 114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\ HUBP_SF 115 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\ HUBP_SF 116 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh) HUBP_SF 121 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ HUBP_SF 122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ HUBP_SF 123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh) HUBP_SF 128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ HUBP_SF 129 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ HUBP_SF 130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh) HUBP_SF 47 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ HUBP_SF 48 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ HUBP_SF 49 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\ HUBP_SF 50 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\ HUBP_SF 51 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\ HUBP_SF 52 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\ HUBP_SF 53 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\ HUBP_SF 54 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \ HUBP_SF 55 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ HUBP_SF 56 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ HUBP_SF 57 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ HUBP_SF 58 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ HUBP_SF 59 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ HUBP_SF 60 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ HUBP_SF 61 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ HUBP_SF 62 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ HUBP_SF 63 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ HUBP_SF 64 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ HUBP_SF 65 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ HUBP_SF 66 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ HUBP_SF 67 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ HUBP_SF 68 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ HUBP_SF 69 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \ HUBP_SF 70 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \ HUBP_SF 71 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \ HUBP_SF 72 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \ HUBP_SF 73 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \ HUBP_SF 74 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \ HUBP_SF 75 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \ HUBP_SF 76 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \ HUBP_SF 77 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \ HUBP_SF 78 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \ HUBP_SF 79 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \ HUBP_SF 80 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \ HUBP_SF 81 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\ HUBP_SF 82 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\ HUBP_SF 83 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\ HUBP_SF 84 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\ HUBP_SF 85 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\ HUBP_SF 86 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\ HUBP_SF 87 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\ HUBP_SF 88 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\ HUBP_SF 89 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\ HUBP_SF 90 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\ HUBP_SF 91 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\ HUBP_SF 92 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, mask_sh),\ HUBP_SF 93 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, mask_sh),\ HUBP_SF 94 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_5, REFCYC_PER_PTE_GROUP_FLIP_C, mask_sh),\ HUBP_SF 95 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\ HUBP_SF 96 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\ HUBP_SF 97 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\ HUBP_SF 98 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh) HUBP_SF 102 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh)