AMDGPU_TILING_GET 1142 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 	    AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
AMDGPU_TILING_GET 1880 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
AMDGPU_TILING_GET 1970 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
AMDGPU_TILING_GET 1973 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
AMDGPU_TILING_GET 1974 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
AMDGPU_TILING_GET 1975 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
AMDGPU_TILING_GET 1976 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
AMDGPU_TILING_GET 1977 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
AMDGPU_TILING_GET 1990 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
AMDGPU_TILING_GET 1922 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
AMDGPU_TILING_GET 2012 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
AMDGPU_TILING_GET 2015 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
AMDGPU_TILING_GET 2016 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
AMDGPU_TILING_GET 2017 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
AMDGPU_TILING_GET 2018 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
AMDGPU_TILING_GET 2019 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
AMDGPU_TILING_GET 2032 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
AMDGPU_TILING_GET 1917 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
AMDGPU_TILING_GET 1920 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
AMDGPU_TILING_GET 1921 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
AMDGPU_TILING_GET 1922 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
AMDGPU_TILING_GET 1923 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
AMDGPU_TILING_GET 1924 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
AMDGPU_TILING_GET 1932 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
AMDGPU_TILING_GET 1936 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
AMDGPU_TILING_GET 1809 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
AMDGPU_TILING_GET 1891 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
AMDGPU_TILING_GET 1894 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
AMDGPU_TILING_GET 1895 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
AMDGPU_TILING_GET 1896 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
AMDGPU_TILING_GET 1897 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
AMDGPU_TILING_GET 1898 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
AMDGPU_TILING_GET 1907 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
AMDGPU_TILING_GET 2692 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
AMDGPU_TILING_GET 2712 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
AMDGPU_TILING_GET 2713 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
AMDGPU_TILING_GET 2752 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
AMDGPU_TILING_GET 2824 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
AMDGPU_TILING_GET 2827 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
AMDGPU_TILING_GET 2828 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
AMDGPU_TILING_GET 2829 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
AMDGPU_TILING_GET 2830 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
AMDGPU_TILING_GET 2831 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
AMDGPU_TILING_GET 2843 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
AMDGPU_TILING_GET 2849 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
AMDGPU_TILING_GET 2877 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);