HIWORD_UPDATE     165 drivers/clk/rockchip/clk-cpu.c 		writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask,
HIWORD_UPDATE     167 drivers/clk/rockchip/clk-cpu.c 		       HIWORD_UPDATE(reg_data->mux_core_alt,
HIWORD_UPDATE     173 drivers/clk/rockchip/clk-cpu.c 		writel(HIWORD_UPDATE(reg_data->mux_core_alt,
HIWORD_UPDATE     209 drivers/clk/rockchip/clk-cpu.c 	writel(HIWORD_UPDATE(0, reg_data->div_core_mask,
HIWORD_UPDATE     211 drivers/clk/rockchip/clk-cpu.c 	       HIWORD_UPDATE(reg_data->mux_core_main,
HIWORD_UPDATE      49 drivers/clk/rockchip/clk-inverter.c 		writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift),
HIWORD_UPDATE     138 drivers/clk/rockchip/clk-mmc-phase.c 	writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift),
HIWORD_UPDATE     203 drivers/clk/rockchip/clk-pll.c 	writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
HIWORD_UPDATE     205 drivers/clk/rockchip/clk-pll.c 		       HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK,
HIWORD_UPDATE     209 drivers/clk/rockchip/clk-pll.c 	writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK,
HIWORD_UPDATE     211 drivers/clk/rockchip/clk-pll.c 		       HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK,
HIWORD_UPDATE     213 drivers/clk/rockchip/clk-pll.c 		       HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK,
HIWORD_UPDATE     261 drivers/clk/rockchip/clk-pll.c 	writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
HIWORD_UPDATE     272 drivers/clk/rockchip/clk-pll.c 	writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,
HIWORD_UPDATE     434 drivers/clk/rockchip/clk-pll.c 	writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0),
HIWORD_UPDATE     438 drivers/clk/rockchip/clk-pll.c 	writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK,
HIWORD_UPDATE     440 drivers/clk/rockchip/clk-pll.c 	       HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK,
HIWORD_UPDATE     444 drivers/clk/rockchip/clk-pll.c 	writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK,
HIWORD_UPDATE     447 drivers/clk/rockchip/clk-pll.c 	writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK,
HIWORD_UPDATE     452 drivers/clk/rockchip/clk-pll.c 	writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0),
HIWORD_UPDATE     494 drivers/clk/rockchip/clk-pll.c 	writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0),
HIWORD_UPDATE     505 drivers/clk/rockchip/clk-pll.c 	writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN,
HIWORD_UPDATE     680 drivers/clk/rockchip/clk-pll.c 	writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,
HIWORD_UPDATE     684 drivers/clk/rockchip/clk-pll.c 	writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK,
HIWORD_UPDATE     686 drivers/clk/rockchip/clk-pll.c 		       HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK,
HIWORD_UPDATE     688 drivers/clk/rockchip/clk-pll.c 		       HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK,
HIWORD_UPDATE     698 drivers/clk/rockchip/clk-pll.c 	writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK,
HIWORD_UPDATE     740 drivers/clk/rockchip/clk-pll.c 	writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0),
HIWORD_UPDATE     751 drivers/clk/rockchip/clk-pll.c 	writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,
HIWORD_UPDATE      81 drivers/clk/rockchip/clk-px30.c 	.val = HIWORD_UPDATE(_aclk_core, PX30_DIV_ACLKM_MASK,		\
HIWORD_UPDATE      83 drivers/clk/rockchip/clk-px30.c 	       HIWORD_UPDATE(_pclk_dbg, PX30_DIV_PCLK_DBG_MASK,	\
HIWORD_UPDATE      86 drivers/clk/rockchip/clk-rk3036.c 		.val = HIWORD_UPDATE(_core_periph_div, RK3036_DIV_PERI_MASK,	\
HIWORD_UPDATE     450 drivers/clk/rockchip/clk-rk3036.c 	writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10),
HIWORD_UPDATE      83 drivers/clk/rockchip/clk-rk3128.c 	.val = HIWORD_UPDATE(_pclk_dbg_div, RK3128_DIV_PERI_MASK,	\
HIWORD_UPDATE      85 drivers/clk/rockchip/clk-rk3128.c 	       HIWORD_UPDATE(_core_aclk_div, RK3128_DIV_ACLK_MASK,	\
HIWORD_UPDATE     112 drivers/clk/rockchip/clk-rk3188.c 		.val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \
HIWORD_UPDATE     118 drivers/clk/rockchip/clk-rk3188.c 		.val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \
HIWORD_UPDATE     120 drivers/clk/rockchip/clk-rk3188.c 		       HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \
HIWORD_UPDATE     122 drivers/clk/rockchip/clk-rk3188.c 		       HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \
HIWORD_UPDATE     124 drivers/clk/rockchip/clk-rk3188.c 		       HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK,	\
HIWORD_UPDATE     163 drivers/clk/rockchip/clk-rk3188.c 		.val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\
HIWORD_UPDATE      84 drivers/clk/rockchip/clk-rk3228.c 		.val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK,	\
HIWORD_UPDATE      86 drivers/clk/rockchip/clk-rk3228.c 		       HIWORD_UPDATE(_core_aclk_div, RK3228_DIV_ACLK_MASK,	\
HIWORD_UPDATE     133 drivers/clk/rockchip/clk-rk3288.c 		.val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \
HIWORD_UPDATE     135 drivers/clk/rockchip/clk-rk3288.c 		       HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \
HIWORD_UPDATE     141 drivers/clk/rockchip/clk-rk3288.c 		.val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK,	\
HIWORD_UPDATE     143 drivers/clk/rockchip/clk-rk3288.c 		       HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK,	\
HIWORD_UPDATE     145 drivers/clk/rockchip/clk-rk3288.c 		       HIWORD_UPDATE(_pclk_dbg_pre,			\
HIWORD_UPDATE      77 drivers/clk/rockchip/clk-rk3308.c 	.val = HIWORD_UPDATE(_aclk_core, RK3308_DIV_ACLKM_MASK,		\
HIWORD_UPDATE      79 drivers/clk/rockchip/clk-rk3308.c 	       HIWORD_UPDATE(_pclk_dbg, RK3308_DIV_PCLK_DBG_MASK,	\
HIWORD_UPDATE      96 drivers/clk/rockchip/clk-rk3328.c 	.val = HIWORD_UPDATE(_aclk_core, RK3328_DIV_ACLKM_MASK,		\
HIWORD_UPDATE      98 drivers/clk/rockchip/clk-rk3328.c 	       HIWORD_UPDATE(_pclk_dbg, RK3328_DIV_PCLK_DBG_MASK,	\
HIWORD_UPDATE     186 drivers/clk/rockchip/clk-rk3368.c 		.val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK,	\
HIWORD_UPDATE     192 drivers/clk/rockchip/clk-rk3368.c 		.val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK,	\
HIWORD_UPDATE     194 drivers/clk/rockchip/clk-rk3368.c 		       HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK,	\
HIWORD_UPDATE     321 drivers/clk/rockchip/clk-rk3399.c 		.val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK,	\
HIWORD_UPDATE     327 drivers/clk/rockchip/clk-rk3399.c 		.val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK,	\
HIWORD_UPDATE     329 drivers/clk/rockchip/clk-rk3399.c 		       HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK,	\
HIWORD_UPDATE      75 drivers/clk/rockchip/clk-rv1108.c 		.val = HIWORD_UPDATE(_core_peri_div, RV1108_DIV_CORE_MASK,\
HIWORD_UPDATE     448 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 	.lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
HIWORD_UPDATE     449 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 	.lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
HIWORD_UPDATE     455 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 	.lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
HIWORD_UPDATE     456 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c 	.lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
HIWORD_UPDATE     996 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c 		.lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
HIWORD_UPDATE     997 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c 		.lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
HIWORD_UPDATE    1004 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c 		.lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
HIWORD_UPDATE    1005 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c 		.lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
HIWORD_UPDATE    1016 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c 		.lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
HIWORD_UPDATE    1017 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c 		.lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
HIWORD_UPDATE    1021 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c 		.lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
HIWORD_UPDATE    1032 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c 		.lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
HIWORD_UPDATE    1033 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c 		.lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,
HIWORD_UPDATE    1037 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c 		.lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
HIWORD_UPDATE    1043 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c 		.lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ |
HIWORD_UPDATE    1050 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c 		.enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
HIWORD_UPDATE     339 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 		HIWORD_UPDATE(RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |
HIWORD_UPDATE     346 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 		HIWORD_UPDATE(RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK,
HIWORD_UPDATE     361 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 			HIWORD_UPDATE(RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V,
HIWORD_UPDATE     366 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 			HIWORD_UPDATE(0, RK3328_HDMI_SDA_5V |
HIWORD_UPDATE     380 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 		HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V |
HIWORD_UPDATE     385 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 		HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF |
HIWORD_UPDATE     390 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 		HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK,
HIWORD_UPDATE     420 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 	.lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
HIWORD_UPDATE     421 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 	.lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SEL, RK3288_HDMI_LCDC_SEL),
HIWORD_UPDATE     457 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 	.lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL),
HIWORD_UPDATE     458 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 	.lcdsel_lit = HIWORD_UPDATE(RK3399_HDMI_LCDC_SEL, RK3399_HDMI_LCDC_SEL),
HIWORD_UPDATE     158 drivers/mmc/host/sdhci-of-arasan.c 				   HIWORD_UPDATE(val, GENMASK(width, 0),
HIWORD_UPDATE     144 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
HIWORD_UPDATE     145 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
HIWORD_UPDATE     253 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3228_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 7)
HIWORD_UPDATE     254 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3228_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
HIWORD_UPDATE     399 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3288_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 7)
HIWORD_UPDATE     400 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3288_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
HIWORD_UPDATE     491 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3328_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 7)
HIWORD_UPDATE     492 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3328_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
HIWORD_UPDATE     643 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3366_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
HIWORD_UPDATE     644 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3366_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
HIWORD_UPDATE     754 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3368_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
HIWORD_UPDATE     755 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3368_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
HIWORD_UPDATE     865 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3399_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
HIWORD_UPDATE     866 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK3399_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
HIWORD_UPDATE    1012 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK_GRF_CON2_MACPHY_ID		HIWORD_UPDATE(0x1234, 0xffff, 0)
HIWORD_UPDATE    1013 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define RK_GRF_CON3_MACPHY_ID		HIWORD_UPDATE(0x35, 0x3f, 0)
HIWORD_UPDATE      22 drivers/pci/controller/pcie-rockchip.h #define HIWORD_UPDATE_BIT(val)		HIWORD_UPDATE(val, val)
HIWORD_UPDATE      32 drivers/pci/controller/pcie-rockchip.h #define   PCIE_CLIENT_CONF_DISABLE       HIWORD_UPDATE(0x0001, 0)
HIWORD_UPDATE      35 drivers/pci/controller/pcie-rockchip.h #define   PCIE_CLIENT_CONF_LANE_NUM(x)	  HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
HIWORD_UPDATE      37 drivers/pci/controller/pcie-rockchip.h #define   PCIE_CLIENT_MODE_EP            HIWORD_UPDATE(0x0040, 0)
HIWORD_UPDATE      38 drivers/pci/controller/pcie-rockchip.h #define   PCIE_CLIENT_GEN_SEL_1		  HIWORD_UPDATE(0x0080, 0)
HIWORD_UPDATE     100 drivers/phy/rockchip/phy-rockchip-emmc.c 		     HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
HIWORD_UPDATE     105 drivers/phy/rockchip/phy-rockchip-emmc.c 		     HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
HIWORD_UPDATE     158 drivers/phy/rockchip/phy-rockchip-emmc.c 		     HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
HIWORD_UPDATE     181 drivers/phy/rockchip/phy-rockchip-emmc.c 		     HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK,
HIWORD_UPDATE     187 drivers/phy/rockchip/phy-rockchip-emmc.c 		     HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
HIWORD_UPDATE     280 drivers/phy/rockchip/phy-rockchip-emmc.c 		     HIWORD_UPDATE(rk_phy->drive_impedance,
HIWORD_UPDATE     287 drivers/phy/rockchip/phy-rockchip-emmc.c 		     HIWORD_UPDATE(PHYCTRL_OTAPDLYENA,
HIWORD_UPDATE     294 drivers/phy/rockchip/phy-rockchip-emmc.c 		     HIWORD_UPDATE(4,
HIWORD_UPDATE     104 drivers/phy/rockchip/phy-rockchip-pcie.c 		     HIWORD_UPDATE(data,
HIWORD_UPDATE     107 drivers/phy/rockchip/phy-rockchip-pcie.c 		     HIWORD_UPDATE(addr,
HIWORD_UPDATE     112 drivers/phy/rockchip/phy-rockchip-pcie.c 		     HIWORD_UPDATE(PHY_CFG_WR_ENABLE,
HIWORD_UPDATE     117 drivers/phy/rockchip/phy-rockchip-pcie.c 		     HIWORD_UPDATE(PHY_CFG_WR_DISABLE,
HIWORD_UPDATE     128 drivers/phy/rockchip/phy-rockchip-pcie.c 		     HIWORD_UPDATE(addr,
HIWORD_UPDATE     147 drivers/phy/rockchip/phy-rockchip-pcie.c 		     HIWORD_UPDATE(PHY_LANE_IDLE_OFF,
HIWORD_UPDATE     168 drivers/phy/rockchip/phy-rockchip-pcie.c 		     HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
HIWORD_UPDATE     195 drivers/phy/rockchip/phy-rockchip-pcie.c 		     HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
HIWORD_UPDATE     201 drivers/phy/rockchip/phy-rockchip-pcie.c 		     HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
HIWORD_UPDATE     252 drivers/phy/rockchip/phy-rockchip-pcie.c 		     HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
HIWORD_UPDATE      83 drivers/phy/rockchip/phy-rockchip-usb.c 	u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ);
HIWORD_UPDATE     336 drivers/phy/rockchip/phy-rockchip-usb.c 	val = HIWORD_UPDATE(UOC_CON0_COMMON_ON_N
HIWORD_UPDATE     346 drivers/phy/rockchip/phy-rockchip-usb.c 	val = HIWORD_UPDATE(UOC_CON2_SOFT_CON_SEL,
HIWORD_UPDATE     352 drivers/phy/rockchip/phy-rockchip-usb.c 	val = HIWORD_UPDATE(UOC_CON3_UTMI_OPMODE_NODRIVING
HIWORD_UPDATE     384 drivers/phy/rockchip/phy-rockchip-usb.c 	val = HIWORD_UPDATE(RK3188_UOC0_CON0_BYPASSSEL
HIWORD_UPDATE     434 drivers/phy/rockchip/phy-rockchip-usb.c 	val = HIWORD_UPDATE(RK3288_UOC0_CON3_BYPASSSEL
HIWORD_UPDATE      35 drivers/soc/rockchip/grf.c 	{ "jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11) },
HIWORD_UPDATE      46 drivers/soc/rockchip/grf.c 	{ "jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8) },
HIWORD_UPDATE      57 drivers/soc/rockchip/grf.c 	{ "jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8) },
HIWORD_UPDATE      69 drivers/soc/rockchip/grf.c 	{ "jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12) },
HIWORD_UPDATE      70 drivers/soc/rockchip/grf.c 	{ "pwm select", RK3288_GRF_SOC_CON2, HIWORD_UPDATE(1, 1, 0) },
HIWORD_UPDATE      81 drivers/soc/rockchip/grf.c 	{ "jtag switching", RK3328_GRF_SOC_CON4, HIWORD_UPDATE(0, 1, 12) },
HIWORD_UPDATE      92 drivers/soc/rockchip/grf.c 	{ "jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13) },
HIWORD_UPDATE     103 drivers/soc/rockchip/grf.c 	{ "jtag switching", RK3399_GRF_SOC_CON7, HIWORD_UPDATE(0, 1, 12) },