HIBMC_FIELD       131 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	writel(HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_WIDTH, reg) |
HIBMC_FIELD       132 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	       HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_OFFS, line_l),
HIBMC_FIELD       138 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_FORMAT,
HIBMC_FIELD       243 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_BYPASS, 0);
HIBMC_FIELD       244 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POWER, 1);
HIBMC_FIELD       245 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_INPUT, 0);
HIBMC_FIELD       246 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POD, pll.POD);
HIBMC_FIELD       247 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_OD, pll.OD);
HIBMC_FIELD       248 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_N, pll.N);
HIBMC_FIELD       249 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_M, pll.M);
HIBMC_FIELD       333 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_TOP, 0) |
HIBMC_FIELD       334 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	       HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_LEFT, 0),
HIBMC_FIELD       337 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM, y - 1) |
HIBMC_FIELD       338 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	       HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_RIGHT, x - 1),
HIBMC_FIELD       371 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	writel(HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_TOTAL, mode->htotal - 1) |
HIBMC_FIELD       372 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	       HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_DISP_END, mode->hdisplay - 1),
HIBMC_FIELD       375 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	writel(HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_WIDTH, width) |
HIBMC_FIELD       376 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	       HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_START, mode->hsync_start - 1),
HIBMC_FIELD       379 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	writel(HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_TOTAL, mode->vtotal - 1) |
HIBMC_FIELD       380 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	       HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_DISP_END, mode->vdisplay - 1),
HIBMC_FIELD       383 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	writel(HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_HEIGHT, height) |
HIBMC_FIELD       384 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	       HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_START, mode->vsync_start - 1),
HIBMC_FIELD       387 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	val = HIBMC_FIELD(HIBMC_CRT_DISP_CTL_VSYNC_PHASE, 0);
HIBMC_FIELD       388 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c 	val |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_HSYNC_PHASE, 0);
HIBMC_FIELD       146 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c 	control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_MODE, power_mode);
HIBMC_FIELD       147 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c 	control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_OSC_INPUT, input);