HHI_HDMI_PLL_CNTL 165 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 170 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 175 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 185 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 190 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 213 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 218 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 223 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 239 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 244 drivers/clk/meson/gxbb.c .reg_off = HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 320 drivers/clk/meson/gxbb.c .offset = HHI_HDMI_PLL_CNTL + 8, HHI_HDMI_PLL_CNTL 338 drivers/clk/meson/gxbb.c .offset = HHI_HDMI_PLL_CNTL + 8, HHI_HDMI_PLL_CNTL 356 drivers/clk/meson/gxbb.c .offset = HHI_HDMI_PLL_CNTL + 8, HHI_HDMI_PLL_CNTL 246 drivers/gpu/drm/meson/meson_vclk.c regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800023d); HHI_HDMI_PLL_CNTL 252 drivers/gpu/drm/meson/meson_vclk.c regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4800023d); HHI_HDMI_PLL_CNTL 255 drivers/gpu/drm/meson/meson_vclk.c regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, HHI_HDMI_PLL_CNTL 259 drivers/gpu/drm/meson/meson_vclk.c regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000027b); HHI_HDMI_PLL_CNTL 267 drivers/gpu/drm/meson/meson_vclk.c regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 269 drivers/gpu/drm/meson/meson_vclk.c regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 273 drivers/gpu/drm/meson/meson_vclk.c regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, HHI_HDMI_PLL_CNTL 276 drivers/gpu/drm/meson/meson_vclk.c regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7); HHI_HDMI_PLL_CNTL 283 drivers/gpu/drm/meson/meson_vclk.c regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x3a0504f7); HHI_HDMI_PLL_CNTL 284 drivers/gpu/drm/meson/meson_vclk.c regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7); HHI_HDMI_PLL_CNTL 287 drivers/gpu/drm/meson/meson_vclk.c regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, HHI_HDMI_PLL_CNTL 459 drivers/gpu/drm/meson/meson_vclk.c regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000200 | m); HHI_HDMI_PLL_CNTL 472 drivers/gpu/drm/meson/meson_vclk.c regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 476 drivers/gpu/drm/meson/meson_vclk.c regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 480 drivers/gpu/drm/meson/meson_vclk.c regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000200 | m); HHI_HDMI_PLL_CNTL 488 drivers/gpu/drm/meson/meson_vclk.c regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 490 drivers/gpu/drm/meson/meson_vclk.c regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 494 drivers/gpu/drm/meson/meson_vclk.c regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, HHI_HDMI_PLL_CNTL 497 drivers/gpu/drm/meson/meson_vclk.c regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x0b3a0400 | m); HHI_HDMI_PLL_CNTL 501 drivers/gpu/drm/meson/meson_vclk.c regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 531 drivers/gpu/drm/meson/meson_vclk.c regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 535 drivers/gpu/drm/meson/meson_vclk.c regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 540 drivers/gpu/drm/meson/meson_vclk.c HHI_HDMI_PLL_CNTL, val, HHI_HDMI_PLL_CNTL 556 drivers/gpu/drm/meson/meson_vclk.c regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 567 drivers/gpu/drm/meson/meson_vclk.c regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, HHI_HDMI_PLL_CNTL 578 drivers/gpu/drm/meson/meson_vclk.c regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,