HDMI_VBI_PACKET_CONTROL 1584 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); HDMI_VBI_PACKET_CONTROL 1617 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ HDMI_VBI_PACKET_CONTROL 1618 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ HDMI_VBI_PACKET_CONTROL 1619 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ HDMI_VBI_PACKET_CONTROL 1626 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); HDMI_VBI_PACKET_CONTROL 1659 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ HDMI_VBI_PACKET_CONTROL 1660 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ HDMI_VBI_PACKET_CONTROL 1661 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ HDMI_VBI_PACKET_CONTROL 1384 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); HDMI_VBI_PACKET_CONTROL 1385 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); HDMI_VBI_PACKET_CONTROL 1386 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); HDMI_VBI_PACKET_CONTROL 647 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, HDMI_VBI_PACKET_CONTROL 74 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \ HDMI_VBI_PACKET_CONTROL 140 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\ HDMI_VBI_PACKET_CONTROL 141 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\ HDMI_VBI_PACKET_CONTROL 142 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\ HDMI_VBI_PACKET_CONTROL 677 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_VBI_PACKET_CONTROL; HDMI_VBI_PACKET_CONTROL 582 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, HDMI_VBI_PACKET_CONTROL 64 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \ HDMI_VBI_PACKET_CONTROL 148 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_VBI_PACKET_CONTROL; HDMI_VBI_PACKET_CONTROL 311 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_VBI_PACKET_CONTROL + offset,