HDMI_INFOFRAME_CONTROL1 1636 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
HDMI_INFOFRAME_CONTROL1 1714 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
HDMI_INFOFRAME_CONTROL1 1678 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
HDMI_INFOFRAME_CONTROL1 1756 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
HDMI_INFOFRAME_CONTROL1 1466 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1,
HDMI_INFOFRAME_CONTROL1 1579 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
HDMI_INFOFRAME_CONTROL1  657 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
HDMI_INFOFRAME_CONTROL1  771 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,
HDMI_INFOFRAME_CONTROL1   73 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
HDMI_INFOFRAME_CONTROL1  145 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
HDMI_INFOFRAME_CONTROL1  153 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\
HDMI_INFOFRAME_CONTROL1  676 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t HDMI_INFOFRAME_CONTROL1;
HDMI_INFOFRAME_CONTROL1  592 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
HDMI_INFOFRAME_CONTROL1   63 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
HDMI_INFOFRAME_CONTROL1  147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	uint32_t HDMI_INFOFRAME_CONTROL1;
HDMI_INFOFRAME_CONTROL1  222 drivers/gpu/drm/radeon/evergreen_hdmi.c 	WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,