HDMI_INFOFRAME_CONTROL0 1624 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
HDMI_INFOFRAME_CONTROL0 1626 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
HDMI_INFOFRAME_CONTROL0 1708 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
HDMI_INFOFRAME_CONTROL0 1710 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
HDMI_INFOFRAME_CONTROL0 1666 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
HDMI_INFOFRAME_CONTROL0 1668 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
HDMI_INFOFRAME_CONTROL0 1750 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
HDMI_INFOFRAME_CONTROL0 1752 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
HDMI_INFOFRAME_CONTROL0 1572 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
HDMI_INFOFRAME_CONTROL0 1573 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
HDMI_INFOFRAME_CONTROL0 1574 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
HDMI_INFOFRAME_CONTROL0 1575 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
HDMI_INFOFRAME_CONTROL0 1587 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0);
HDMI_INFOFRAME_CONTROL0 1588 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0);
HDMI_INFOFRAME_CONTROL0 1589 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0);
HDMI_INFOFRAME_CONTROL0 1590 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0);
HDMI_INFOFRAME_CONTROL0  653 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
HDMI_INFOFRAME_CONTROL0  767 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
HDMI_INFOFRAME_CONTROL0  775 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
HDMI_INFOFRAME_CONTROL0   72 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
HDMI_INFOFRAME_CONTROL0  143 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
HDMI_INFOFRAME_CONTROL0  151 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\
HDMI_INFOFRAME_CONTROL0  152 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\
HDMI_INFOFRAME_CONTROL0  675 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t HDMI_INFOFRAME_CONTROL0;
HDMI_INFOFRAME_CONTROL0  588 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
HDMI_INFOFRAME_CONTROL0   62 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
HDMI_INFOFRAME_CONTROL0  146 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	uint32_t HDMI_INFOFRAME_CONTROL0;
HDMI_INFOFRAME_CONTROL0  414 drivers/gpu/drm/radeon/evergreen_hdmi.c 			WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,
HDMI_INFOFRAME_CONTROL0  422 drivers/gpu/drm/radeon/evergreen_hdmi.c 			WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,
HDMI_INFOFRAME_CONTROL0  431 drivers/gpu/drm/radeon/evergreen_hdmi.c 		WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0);