HDMI_GC_CONT     1619 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
HDMI_GC_CONT     1661 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
HDMI_GC_CONT     1386 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1);
HDMI_GC_CONT      648 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		HDMI_GC_CONT, 1,
HDMI_GC_CONT      140 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
HDMI_GC_CONT      227 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
HDMI_GC_CONT      413 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint8_t HDMI_GC_CONT;
HDMI_GC_CONT      544 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t HDMI_GC_CONT;
HDMI_GC_CONT      583 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		HDMI_GC_CONT, 1,
HDMI_GC_CONT      195 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
HDMI_GC_CONT      377 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	type HDMI_GC_CONT;\
HDMI_GC_CONT      314 drivers/gpu/drm/radeon/evergreen_hdmi.c 		HDMI_GC_CONT);		/* send general control packets every frame */