HDMI_DDC_CTRL_SW_STATUS_RESET  328 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c 		reg_val |= HDMI_DDC_CTRL_SW_STATUS_RESET;
HDMI_DDC_CTRL_SW_STATUS_RESET  334 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c 		reg_val &= ~HDMI_DDC_CTRL_SW_STATUS_RESET;
HDMI_DDC_CTRL_SW_STATUS_RESET   22 drivers/gpu/drm/msm/hdmi/hdmi_i2c.c 			HDMI_DDC_CTRL_SW_STATUS_RESET);