HDMI_CON6          73 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
HDMI_CON6          74 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
HDMI_CON6          77 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
HDMI_CON6         100 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
HDMI_CON6         103 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
HDMI_CON6         104 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
HDMI_CON6         128 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_PREDIV_MASK);
HDMI_CON6         129 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
HDMI_CON6         131 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC),
HDMI_CON6         133 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR),
HDMI_CON6         137 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL),
HDMI_CON6         139 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV),
HDMI_CON6         143 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP),
HDMI_CON6         145 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC),
HDMI_CON6         147 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR),
HDMI_CON6         168 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	val = (readl(hdmi_phy->regs + HDMI_CON6)
HDMI_CON6         182 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	val = (readl(hdmi_phy->regs + HDMI_CON6)
HDMI_CON6         206 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
HDMI_CON6         207 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
HDMI_CON6         210 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
HDMI_CON6         230 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
HDMI_CON6         233 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
HDMI_CON6         234 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
HDMI_CON6         275 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,