HDMI_ACR_PACKET_CONTROL 1656 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
HDMI_ACR_PACKET_CONTROL 1659 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
HDMI_ACR_PACKET_CONTROL 1661 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
HDMI_ACR_PACKET_CONTROL 1698 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
HDMI_ACR_PACKET_CONTROL 1701 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
HDMI_ACR_PACKET_CONTROL 1703 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
HDMI_ACR_PACKET_CONTROL 1401 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
HDMI_ACR_PACKET_CONTROL 1402 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE,
HDMI_ACR_PACKET_CONTROL 1383 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
HDMI_ACR_PACKET_CONTROL   76 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
HDMI_ACR_PACKET_CONTROL  178 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
HDMI_ACR_PACKET_CONTROL  179 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
HDMI_ACR_PACKET_CONTROL  180 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
HDMI_ACR_PACKET_CONTROL  679 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t HDMI_ACR_PACKET_CONTROL;
HDMI_ACR_PACKET_CONTROL 1318 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
HDMI_ACR_PACKET_CONTROL   66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
HDMI_ACR_PACKET_CONTROL  150 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	uint32_t HDMI_ACR_PACKET_CONTROL;
HDMI_ACR_PACKET_CONTROL   80 drivers/gpu/drm/radeon/evergreen_hdmi.c 		WREG32(HDMI_ACR_PACKET_CONTROL + offset,
HDMI_ACR_PACKET_CONTROL   83 drivers/gpu/drm/radeon/evergreen_hdmi.c 		WREG32(HDMI_ACR_PACKET_CONTROL + offset,