HDMI_ACR_AUTO_SEND 1661 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); HDMI_ACR_AUTO_SEND 1703 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); HDMI_ACR_AUTO_SEND 1401 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); HDMI_ACR_AUTO_SEND 1384 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c HDMI_ACR_AUTO_SEND, 1, HDMI_ACR_AUTO_SEND 178 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\ HDMI_ACR_AUTO_SEND 258 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\ HDMI_ACR_AUTO_SEND 454 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint8_t HDMI_ACR_AUTO_SEND; HDMI_ACR_AUTO_SEND 585 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_ACR_AUTO_SEND; HDMI_ACR_AUTO_SEND 1319 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c HDMI_ACR_AUTO_SEND, 1, HDMI_ACR_AUTO_SEND 230 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\ HDMI_ACR_AUTO_SEND 420 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h type HDMI_ACR_AUTO_SEND;\ HDMI_ACR_AUTO_SEND 81 drivers/gpu/drm/radeon/evergreen_hdmi.c HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ HDMI_ACR_AUTO_SEND 85 drivers/gpu/drm/radeon/evergreen_hdmi.c HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */