HDMI_ACR_48_1    1492 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
HDMI_ACR_48_1    1534 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
HDMI_ACR_48_1    1424 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
HDMI_ACR_48_1    1415 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
HDMI_ACR_48_1      82 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(HDMI_ACR_48_1, DIG, id),\
HDMI_ACR_48_1     186 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
HDMI_ACR_48_1     685 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t HDMI_ACR_48_1;
HDMI_ACR_48_1    1350 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
HDMI_ACR_48_1      72 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(HDMI_ACR_48_1, DIG, id),\
HDMI_ACR_48_1     156 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	uint32_t HDMI_ACR_48_1;
HDMI_ACR_48_1      94 drivers/gpu/drm/radeon/evergreen_hdmi.c 	WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz);