HDMI_ACR_44_1 1485 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); HDMI_ACR_44_1 1527 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); HDMI_ACR_44_1 1417 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); HDMI_ACR_44_1 1409 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); HDMI_ACR_44_1 80 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SRI(HDMI_ACR_44_1, DIG, id),\ HDMI_ACR_44_1 184 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\ HDMI_ACR_44_1 683 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_ACR_44_1; HDMI_ACR_44_1 1344 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); HDMI_ACR_44_1 70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SRI(HDMI_ACR_44_1, DIG, id),\ HDMI_ACR_44_1 154 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_ACR_44_1; HDMI_ACR_44_1 91 drivers/gpu/drm/radeon/evergreen_hdmi.c WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);